Class Ab amplifier second stage

Hi Everyone :-o

Why in class-ab amplifier second stage of two stage amplifier there are two of miller capacitors or two cascode miller capacitors. I have looked to the r/r amplifier (see attachment)

:wink::wink:

Hi, those are not "cascode miller capacitors", this is not an existing phrase. This is a rail to rail amplifier, everything is duplicated, not just the capacitors. But because it is rail to rail those also should be duplicated, so they can ensure stability at lower and higher output voltage swings too.

frankrose said:

Hi, those are not "cascode miller capacitors", this is not an existing phrase. This is a rail to rail amplifier, everything is duplicated, not just the capacitors. But because it is rail to rail those also should be duplicated, so they can ensure stability at lower and higher output voltage swings too.

Click to expand...

Thank you for reply, but why there are splitting to capacitors, also this mention in (Compact Low-Voltage Power-Efficient
Operational Amplifier Cells for VLSI) for Huijsing

In a class A amplifier, there is only one device in the signal path (the complementary one is nothing more than constant current source).
In class AB, both n- and p-fets can be the amplifying devices in the signal path, so both are covered by the compensation loop. With only one cap, you would be able to see an oscillations if the signals would exceed some level.

Dominik Przyborowski said:

In a class A amplifier, there is only one device in the signal path (the complementary one is nothing more than constant current source).
In class AB, both n- and p-fets can be the amplifying devices in the signal path, so both are covered by the compensation loop. With only one cap, you would be able to see an oscillations if the signals would exceed some level.

Click to expand...

There are many class AB amplifiers with 1 compensation capacitor, not this is the point I think, but I am not sure.
The amplifier is rail to rail, input and output also. If the input voltage is too high it pushes the NMOS diff. pair or the top PMOS devices into triode region in the 1st stage.
It decreases the gain by decreasing the resistance at the upper transistors common nodes (at the "Isum" nodes at the top).
Thus more part of the feedback current from the top capacitor will flow in other directions like in normal operation, and the effect is equal with decreased compensation capacitor value. This is not good for stability, because it increases the 1st pole's frequency.
But if it uses an other compensation capacitor at the bottom, those NMOS devices and the PMOS diff. pair are in saturation, so all of the capacitive feedback current can flow in its normal direction, and the stability will be ensured, doesn't matter that the upper Miller capacitor's effective value is decreased.
And it works vica-versa with low input voltages I think. But I am not sure!