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layout problems in voltage divider using diode connected mosfet

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gopalece

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I have designed a voltage divider network using diode connected mosfets(NMOS).The schematic consists of four diode connected mosfets.Middle two transistors substrate terminals are connected to source terminals.Upper transistor substrate terminal is connected to Vdd and Lower transistor Substrate terminal is connected to ground.I am designing layout for it. Substrate terminals are having different potentials.How can I connect substrate terminals in layout
 

As already mentioned in your previous threads, it's not possible in standard CMOS process. Which process are you designing for?
 

Connecting the "upper" NMOS substrate to Vdd
would make it a PN diode (B-S). Leavinf aside that
it also creates a supply-supply short (or low value
resistor) in any standard JI CMOS.

Freedom isn't free - you want 4 terminals worth of
design liberty, you're gonna pay for an upscale substrate.
 

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