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Layer definition in TSMC 65nm

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AllenD

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Hi，
Can anyone help me with where I can find a complete layer definition in TSMC PDK?

I am currently using TSMC 65nm (1p9m_6x1z1u_alrdl) and trying to layout the circuit. In the routing layer selection, I think there are a few layers on top of M9 drawing, namely AP drawing, AP drawing1, RV drawing, PO drawing2.

Though I can find the definition from PO to M10_al rdl, I couldn't find these 4 layer names on the model doc. I am just wonders what are these layers? What is the difference between AP drawing and AP drawing1?

Thanks
Allen
 

PO is "poly".
"AP" is a layer one level up form the topmost "metal" layer - e.g., if your technology is 1p9m, it means AP is the next above M9, i.e. kind of M10.
RV is a via between M9 and AP, most likely.

All this should be documented in the design rule manual - look for it.

I don't know the difference between "drawing" and "drawing2".
 

Hi
Thanks for your reply. I did find the definition of design rule (DR) doc.
But unfortunately, even the DR doc doesn't mention the difference between drawing and drawing1.
I normally thought drawing1,2,3.... layerw are like dummy layers that I can just ignore until I saw that in my routing layer pallet. For example, all the "PO" of transistors are layout in PO drawing layer from the PDK. Then why did the PDK put the PO drawing2 layer in routing layer section?

I am more familiar in ADS and in ADS there is an option to print a 3D view of the layout. Is there a similar to to print this in cadence?

Thanks
Allen
 

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