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best method for control memory in fpga

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jalal.baba

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Hi friends.
I have 6 blocks which write data in a one memory(parallel) but some blocks may want to write in a one address of memory(problem).
whats the best method for this?

14.JPG
 

Hi,

Do the "blocks" work synchronously?
Can you use a write cache or a write FIFO?
Can't you divide the memory... one for each block?

Klaus
 

1-blocks work synchronously.
2-yes I can. what can i use cache or fifo buffer or cache when whole of blocks work synchronously?
3-I don't think because blocks randomly write to memory.
may block6 write to memory(address1) and block 6(address1)
 

Hi,

Seems weird. Are you sure it majes sense?
How do you ensure data integrity...I mean ... sometimes you need to read the contents.how do you ensure that at exactely this time the data is valid?

***
Back to your problem.
If block_write_cycle_time > block_count x RAM_access_time
Then each block may write it's data in a single stage buffer (containing RAM address and data) and a FSM performs the sequential write from buffer to RAM.

6 x (block + buffer) --> FSM --> RAM

Klaus
 

Who is generating the addresses the memory? Are they done by the blocks itself?

3-I don't think because blocks randomly write to memory.
may block6 write to memory(address1) and block 6(address1)

Why can't you have an address decoder in front of your memory such that blocks can *only* WRITE/READ from a set range?
If the above cannot be done, then I think an arbiter needs to decide which block writes to the address.

Above all, instead of us asking questions (because of the lack of proper description) and trying to find out what you want to do, it would be good if can you explain your design scenario in clear, short and punctuated sentences.
 
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This seems not well designed. Why are elements accessing the same resource with no coordination? What is the expected result when two or more write to the same element?
 

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