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Fully Differential Amplifier MISMATCH analysis

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bansal177

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Hi all,

I am designing two stage fully differential amplifier. Both stage are CMFB compensated. My problem is that after first stage only there is so much offset in output of first stage (because of mismatch) Second stage ouputs are going to vdd and ground.

Is there any solution to it.

Waiting for reply urgently.

Thanks,
Amit
 

Auto-zeroing, Choppering, negative feedback, area increasing. There are many solutions, post your system and/or your circuits and write down what you want exactly.
 
By the way, if your amplifier is an AC amplifier use capacitive coupling between the stages. Then DC offset is eliminated.
 

frankrose said:
Auto-zeroing, Choppering, negative feedback, area increasing. There are many solutions, post your system and/or your circuits and write down what you want exactly.
Click to expand...

Hi Frankrose,

Thank you very much for your reply. Please find my circuit below.

My plan right now is

output offset storage autozero method to be used

Please let me know if there is any alternative and best approach

Thanks,
Amit
 

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Hi Frankrose,

It is not AC amplifier. Its inputs are dc signals.

Thanks,
Amit
 

How do you control the gain? Don't bother you if it is changing a lot? If you can use negative feedback you can hold constant the gain and your output wouldn't sit on the gnd or vdd. Isn't it an option, the feedback? Easier than auto-zeroing. You will need clock, choose a clock frequency, design switches and so on...
 
frankrose said:
How do you control the gain? Don't bother you if it is changing a lot? If you can use negative feedback you can hold constant the gain and your output wouldn't sit on the gnd or vdd. Isn't it an option, the feedback? Easier than auto-zeroing. You will need clock, choose a clock frequency, design switches and so on...
Click to expand...

Hi, this opamp is used in a fully differential switch capacitor circuit. In the sampling phase, the opamp is connected in unity negative feedback. So do you think this will solve my problem and output will not swing to vdd/ground when there is mismatch.

Regards,
Amit
 

Yes, if the 2 stages are connected as a unity gain buffer I think mismatch only cause small offset, like n*1mV, but the output won't sit on the vdd or gnd. If you set higher gain the mismatch caused output offset can increase, but the output still shouldn't be 0 or vdd, depends on the closed loop gain. If it operates when the gain is unity you are ok.
 

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