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Innovus CTS for a range of clock

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Anklon

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Lets assume, I have a clock source whose frequency can very within a range (like within 6MHz to 9MHz range).I have a verilog circuit module where I would like to use this clock.

How can I configure Innovus to perform clock tree synthesis and post route synthesis so that this total circuit will not be susceptible to any clock related violation (setup time, hold time etc.) within a particular frequency range? What kind of possible setup should I use ?

thank you for your time.
 

Lets assume, I have a clock source whose frequency can very within a range (like within 6MHz to 9MHz range).I have a verilog circuit module where I would like to use this clock.

How can I configure Innovus to perform clock tree synthesis and post route synthesis so that this total circuit will not be susceptible to any clock related violation (setup time, hold time etc.) within a particular frequency range? What kind of possible setup should I use ?

thank you for your time.

As far as I know, the typical procedure in this kind of situations is to develop the sistem to work in the worst case scenario (the higher frequency).
If you assure that the system works and respect your constraints at the higher frequency, in your case 9MHz, then it will work at 6MHz as well.
 

As far as I know, the typical procedure in this kind of situations is to develop the sistem to work in the worst case scenario (the higher frequency).
If you assure that the system works and respect your constraints at the higher frequency, in your case 9MHz, then it will work at 6MHz as well.

unfortunately this is not always true, there are hold issues that have to be accounted for.

OP: as far as I know, no tool has support for clock 'ranges'. what you need are different clock modes and different SDCs, which will become different corners in your MMMC file. if your setup is right, timing will take care of everything for you.
 

Thanks a lot for the reply. I will surely check out for setting different clock modes in Innovus.

However, just out of curiosity, I would like to know the hold issues that you have mentioned, are likely to occur.

Say, I've set the clock freq to the highest possible value and then done the STA. Innovus will meet the timing constrains(setup, hold etc.) for that frequency across different corners(worst, best etc.). This way, I will be sure that when the circuit is working in ff corner or ss corner, there are no timing violations in the fastest freq. Now say the freq has changed and moved to a lower value. Clearly, there will be no setup violations. Now I would like to ask how would you picture the hold violation in this case?

To summarize, setup time, hold time is the property of the DFFs and related to the clock edge as far as I know. So if the different freqs have same risetime-falltime, aren't they(setup-hold time of the flops) supposed to be the same? Could you please suggest me what I am thinking wrong here?

If you kindly give us a scenario, it will be really great. Thank you once again :)
 

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