Puppet123
Full Member level 6
Hello,
I am laying out a CMOS transistor (with fingered layout) of a quite wide transistor (width = 500um, length = minimum) for high speed mmwave application.
The transistor is not in the RF path and is in the DC path and is drawing 20mA of current.
I have heard of something called vertical layout where you connect transistors vertically with the gate connections vertically applied.
My question: how do I lay out this large width transistor while meeting metal current density rules and what is the proper finger widths and segmentation of the width to meet reliability, and again metal current density rules and have easy routing for the interconnect/signals ?
Thanks.
I am laying out a CMOS transistor (with fingered layout) of a quite wide transistor (width = 500um, length = minimum) for high speed mmwave application.
The transistor is not in the RF path and is in the DC path and is drawing 20mA of current.
I have heard of something called vertical layout where you connect transistors vertically with the gate connections vertically applied.
My question: how do I lay out this large width transistor while meeting metal current density rules and what is the proper finger widths and segmentation of the width to meet reliability, and again metal current density rules and have easy routing for the interconnect/signals ?
Thanks.