+ Post New Thread
Results 1 to 8 of 8
  1. #1
    Advanced Member level 5
    Points: 12,344, Level: 26

    Join Date
    Aug 2011
    Posts
    2,501
    Helped
    288 / 288
    Points
    12,344
    Level
    26

    Modelsim VHDL simulation seems to disobey the hold time principle

    Hello,
    In my design I have this very simple synchronous process:

    Code:
        counting_read_burst : process ( IN_CLOCK , IN_RESET_ASYNCHRONOUS ) is
        begin 
            if IN_RESET_ASYNCHRONOUS = '1' then
    	   counter_selected_read_burst <= ( others => '0' ) ;
            elsif rising_edge ( IN_CLOCK ) then 
    	   if IN_VALID_INFORMATION = '1' then
    		if counter_selected_read_burst = selected_length_read_burst - 1 then
    	         	counter_selected_read_burst <= ( others => '0' ) ;
    		else
    			counter_selected_read_burst <= counter_selected_read_burst + 1 ;    
    		end if ;
               end if ;	
            end if ;        
        end process counting_read_burst ;
    IN_VALID_INFORMATION is a signal that's also generated synchronously - so I expect "counter_selected_read_burst" to increment one cycle AFTER it rises to '1'.
    Unfortunately, this doesn't happen:
    counter_selected_read_burst increments on the same edge as IN_VALID_INFORMATION rises from low to high.

    What's going on??
    I'm completely baffled.

    •   Alt14th April 2018, 18:43

      advertising

        
       

  2. #2
    Advanced Member level 5
    Points: 35,892, Level: 46
    Achievements:
    7 years registered

    Join Date
    Jun 2010
    Posts
    6,567
    Helped
    1914 / 1914
    Points
    35,892
    Level
    46

    Re: Modelsim VHDL simulation seems to disobey the hold time principle

    Without the whole code, we can only guess



  3. #3
    Advanced Member level 5
    Points: 12,344, Level: 26

    Join Date
    Aug 2011
    Posts
    2,501
    Helped
    288 / 288
    Points
    12,344
    Level
    26

    Re: Modelsim VHDL simulation seems to disobey the hold time principle

    So take a guess...
    Can you offer any explanation for this not being a bug ?



    •   Alt14th April 2018, 20:28

      advertising

        
       

  4. #4
    Advanced Member level 3
    Points: 5,108, Level: 16

    Join Date
    Feb 2015
    Posts
    851
    Helped
    244 / 244
    Points
    5,108
    Level
    16

    Re: Modelsim VHDL simulation seems to disobey the hold time principle

    my guess is that it is based on how you generate IN_VALID_INFORMATION, which is not shown.



  5. #5
    Advanced Member level 5
    Points: 35,892, Level: 46
    Achievements:
    7 years registered

    Join Date
    Jun 2010
    Posts
    6,567
    Helped
    1914 / 1914
    Points
    35,892
    Level
    46

    Re: Modelsim VHDL simulation seems to disobey the hold time principle

    This kind of thing usually happens when you think IN_VALID_INFORMATION is synchronous to IN_CLOCK, but actually isnt. Maybe you created it using a clock that has a delta delay wrt IN_CLOCK, or you just used absolute times values to generate it, meaning it changes a delta before the clock edge.

    Or maybe theres another problem.


    1 members found this post helpful.

  6. #6
    Advanced Member level 5
    Points: 12,344, Level: 26

    Join Date
    Aug 2011
    Posts
    2,501
    Helped
    288 / 288
    Points
    12,344
    Level
    26

    Re: Modelsim VHDL simulation seems to disobey the hold time principle

    Nope.
    The clock that drives "OUT_VALID" is absolutely the same one that drives "counter_selected_read_burst".
    I moved the process above one hierarchy up ( just to see what happens ) - and it behaves properly!
    This is very strange.

    Maybe it has something to do with the timing resolution ? or the glbl.v file I'm using ?



  7. #7
    Advanced Member level 5
    Points: 35,892, Level: 46
    Achievements:
    7 years registered

    Join Date
    Jun 2010
    Posts
    6,567
    Helped
    1914 / 1914
    Points
    35,892
    Level
    46

    Re: Modelsim VHDL simulation seems to disobey the hold time principle

    This is why we need to whole code.
    It's clearly a delta problem. Please post the code.



    •   Alt15th April 2018, 07:20

      advertising

        
       

  8. #8
    Advanced Member level 5
    Points: 12,344, Level: 26

    Join Date
    Aug 2011
    Posts
    2,501
    Helped
    288 / 288
    Points
    12,344
    Level
    26

    Re: Modelsim VHDL simulation seems to disobey the hold time principle

    This is why we need to whole code.
    It's clearly a delta problem. Please post the code.
    I'll post it - but it'll take me some time.

    For now, I managed to "fix" the code in a way that clearly points out it's a delta issue:

    This causes faulty behavior:
    Code:
    counting_read_burst : process ( IN_CLOCK , IN_RESET_ASYNCHRONOUS ) is
        begin 
            if IN_RESET_ASYNCHRONOUS = '1' then
    	   counter_selected_read_burst <= ( others => '0' ) ;
            elsif rising_edge ( IN_CLOCK ) then 
    	   if IN_VALID_INFORMATION = '1' then
    		if counter_selected_read_burst = selected_length_read_burst - 1 then
    	         	counter_selected_read_burst <= ( others => '0' ) ;
    		else
    			counter_selected_read_burst <= counter_selected_read_burst + 1 ;    
    		end if ;
               end if ;	
            end if ;        
        end process counting_read_burst ;
    This works flawlessly:
    Code:
    temp_IN_VALID_INFORMATION  <= IN_VALID_INFORMATION ; -- added an intermediate signal (a pure wire) 
    
    counting_read_burst : process ( IN_CLOCK , IN_RESET_ASYNCHRONOUS ) is
        begin 
            if IN_RESET_ASYNCHRONOUS = '1' then
    	   counter_selected_read_burst <= ( others => '0' ) ;
            elsif rising_edge ( IN_CLOCK ) then 
    	   if temp_IN_VALID_INFORMATION = '1' then
    		if counter_selected_read_burst = selected_length_read_burst - 1 then
    	         	counter_selected_read_burst <= ( others => '0' ) ;
    		else
    			counter_selected_read_burst <= counter_selected_read_burst + 1 ;    
    		end if ;
               end if ;	
            end if ;        
        end process counting_read_burst ;



--[[ ]]--