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Simulating Netlist in Modelsim

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javierh.santiago

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Greetings,

I generated a netlist using design Compiler and now I would like to test it in Modelsim by means of a TB. However, when I am running the netlist, the tool can not find the gates (AND, OR, FFs, etc), how can I specify them in order to see the waveforms in modelsim?

I am working with Verilog.


Regards,
Francisco
 
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on the vsim command line add the simulation libraries with the -L <library_name> option.
If you don't already have a compiled simulation library then you'll need to compile the vendors simulation library code into the library using vlog (if library is in Verilog).
 

Expanding on what #2 said, you can do the following.

vsim -f ${path_2_vsim_args.txt} module2simulate

the vsim_arg file can be
-L library1 \
-L library2 \


Therefore you should be able to pull in the library components/models in your simulation.
 
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