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Working in synthesis

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ranayehya

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Hello
I work with synopsys for the first time and some issues I have in running the synthsis


Design 'gng' has '2' unresolved references UID-341
In design 'gng' , Input port'clk' drives wired logic LINT-6
Connot find the design 'gng_ctg' in the library 'Work'LBR-1
Unable to resolve reference 'gng_ctg' in 'gng' LINT-5

and lots of warnings like this
I know these only warnings but after that I have these errors in design setup step


../syn/output/gng.v ; Error Port connection failed VER-500
Verilog parser cannot parse the ../syn/output/gng.v MWNL-047
Current design is not defined UID-4


Any help ?
Thanks in advance
 

It seem to me that your list of input verilog files are not enough.
You need to read ../syn/output/gng_ctg.v also, before reading gng.v.

Have a check if it is the reason.
 

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