alex_fd
Newbie level 5
hello.Is there anyone who could tell me the procedure of design a inductive source degenerated LNA at 2.4GHz?
I am designing a source degenerated LNA. And I used a cascode NMOS .And some collegue told me that at first I should sweep the width of gm nmos while setting its length to minimum?Sweeping the width of the gm nmos can find the curve of the relaiton of NFmin vs. width of gm nmos.but it is not power constrainde .
IF in the power consumption constrained case,how to find the right width of the gm nmos?
And how to design the voltage gain of the LNA?I think the lna must get the gain and nf and power consumption under spec simaltuniously.And I know from book that Gm,eff (Gm from the lna input to the output current)and the Qin(voltage gain from the lna input to the Vgs of the gm mosfet)should be considered.And the parasitic capcitance of the input pad of lna should also be considered
how to consider these factors all ?and is there a design procedure that covers all of it?
thanks a lot
I am designing a source degenerated LNA. And I used a cascode NMOS .And some collegue told me that at first I should sweep the width of gm nmos while setting its length to minimum?Sweeping the width of the gm nmos can find the curve of the relaiton of NFmin vs. width of gm nmos.but it is not power constrainde .
IF in the power consumption constrained case,how to find the right width of the gm nmos?
And how to design the voltage gain of the LNA?I think the lna must get the gain and nf and power consumption under spec simaltuniously.And I know from book that Gm,eff (Gm from the lna input to the output current)and the Qin(voltage gain from the lna input to the Vgs of the gm mosfet)should be considered.And the parasitic capcitance of the input pad of lna should also be considered
how to consider these factors all ?and is there a design procedure that covers all of it?
thanks a lot