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Common Centroid Layout

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Puppet123

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For under or at 65nm CMOS designs, is common centroid layout still necessary for differential pairs in CMOS layout or is interdigitation sufficient ?

I was told that under 0.18um CMOS common centroid is "not necessary".

Is this true ?
 

It depends on what kind of matching you need. You want the best matching possible, then you should go for common centroid, be it any technology. As the spatial gradient mismatch is modeled, common centroid is the safest option.
 
Thanks.

So would it be correct to say it is best to use common centroid where you want low offset and high accuracy structures (enabled by good matching) such as for comparators (differential) and opamps (also differential with differential pairs) for data converter applications and say, wireline applications ?

Where else - or what other circuits - would common centroid layout be useful in besides those I mentioned above ?
 

Puppet123 said:
So would it be correct to say it is best to use common centroid where you want low offset and high accuracy structures (enabled by good matching) such as for comparators (differential) and opamps (also differential with differential pairs) for data converter applications and say, wireline applications ?
Click to expand...

Yes, wherever you need high accuracy, common centroid can be incorporated. The concern would be that the parasitic capacitance will be more than that with simple interdigitisation. So, it is a trade-off between speed and accuracy.

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Okay so it depends on what your needs are and then you would have to see the effect on performance when you do layout, extract and see results and possibly re layout and extract again to get better performance ?

Are there any resources (books, papers, etc) on common centroid layout techniques ? For opamp layout particularly ?
 

Art of analog layout is a good book on analog layout.
 

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