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    setup violation in physical designing

    How to fix the setup violation even after the path is fully optimized ? And commands… :)

    •   Alt12th April 2018, 07:05

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    Re: setup violation in physical designing

    There is no command to "fix" a setup violation. Setup violations indicate a problem with the design, so the design likely needs to be fixed.

    The easiest way to fix setup constraints is to modify the RTL source.
    Failing that, you'll need to ensure all multi-cycle and false paths are set.
    Then worst case you could try a max delay constraint on the path.



    •   Alt12th April 2018, 09:14

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    Re: setup violation in physical designing

    First of all it is important to understand which path in the design is failing, trace it back to RTL code and the verify what are the timing constraints that has been defined for that path in the constraint file.

    So to fix it either you have to modify the logic to satisfy the constraints or relax the constraints, whichever fulfills your design requirements.



    •   Alt12th April 2018, 10:13

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    Re: setup violation in physical designing

    Quote Originally Posted by vinu114 View Post
    How to fix the setup violation even after the path is fully optimized ? And commands… :)
    You want to fix setup violation in "physical designing" ?
    Does it mean you are in Layout phase ?

    1. Check the STA status in early stages
    If you are in layout phase, let check whether this path has violation in the placement phase, or synthesis phase.
    If yes, please give the feedback to front end team also.
    They have responsibility to take care the logic modification.

    If no, this is layout issue. Please check the clock tree synthesis result regarding to clock latencies of this path.

    2. you can make a useful skew to fix it. Just add buffer to change the clock latency to make the path MET.
    But please take care its side-effect.

    3. Please check if your design constraint have size-only/dont-touch attribute applied to the cell on the data path.
    If there are, tool can not make it best effort in term of timing optimization.
    To improve one's brain, the doors are needed over the keys.



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