When can we avoid using reset synchronizer?

We are using reset synchronizers to have flops come out of reset synchronously.

But if inputs to those flops are not changing until much later after the reset deasserts, we do not need reset synchronizer right? Please help confirm.

Thanks

Is the clock to the flop toggling? If the reset is released close to the clock edge , then even if D input is not changing, you will still have issue.

morris_mano said:

If the reset is released close to the clock edge , then even if D input is not changing, you will still have issue.

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Could you please explain why? The actual output from the slave latch is stable right? and when async reset is removed, the output will just get the stable output from the slave latch?

In almost any digital design, you have some registers toggling from the start, e.g. timing generators. They need reset synchronizers to guarantee consistent initial state. The usual solution is to connect the synchronizer to the global reset line.

If so, what is this thread all about?

stanford said:

We are using reset synchronizers to have flops come out of reset synchronously.

But if inputs to those flops are not changing until much later after the reset deasserts, we do not need reset synchronizer right? Please help confirm.

Thanks

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How else can you guarantee that just after power-up the registers are in a known state?

I guess if you use some pull-ups/downs you can do it but thats probably not the best design practice.

FvM said:

In almost any digital design, you have some registers toggling from the start, e.g. timing generators. They need reset synchronizers to guarantee consistent initial state. The usual solution is to connect the synchronizer to the global reset line.

If so, what is this thread all about?

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As I said in my original question, I'm just talking about the flops that don't have inputs toggling from the start.

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mwb said:

How else can you guarantee that just after power-up the registers are in a known state?

I guess if you use some pull-ups/downs you can do it but thats probably not the best design practice.

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Resets guarentee that registers are in a known state. I'm talking about the deassertion of reset.

As I said in my original question, I'm just talking about the flops that don't have inputs toggling from the start.

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I know. But in my view the consideration is pointless for most practical designs, both ASIC and FPGA. If you need the synchronizer for one FF, you can use it for all with no extra effort. A more practical question related to ASIC design is to identify registers that don't need to be reset at all, saving a few transistors and a bit of routing metal.

stanford said:

We are using reset synchronizers to have flops come out of reset synchronously.

But if inputs to those flops are not changing until much later after the reset deasserts, we do not need reset synchronizer right? Please help confirm.

Thanks

Click to expand...

If the flipflop resets to 0 and you have a 0 coming in on the D input then you do not need to synchronize the trailing edge of reset. It will remain at 0 no matter where reset aligns with clock. Same is true with a 1. The vast majority of flops in an embedded system design come out of reset and do nothing but stay in their reset state. You only need to synchronize reset for flops that change state on the very first clock after reset and there are really only a handful of those.

You do not need to design your reset system so that all flops deassert on the same clock. You only need that for the 0.000001% of flops that change state on the first clock. Don't waste your time balancing the entire reset tree for the sake of a few flops. Just make sure that the slowest path on the reset tree finishes well before the first flop has to change states.



John Eaton

When you have no care for reset-release race conditions.

Which is never, if you're smart or responsible for outcomes
(such as test development timetable and test repeatability).

You would want to prove that no register bit changes
and that would take a lot of reset-relative-to-clock
timing challenge cases, which your digital simulator and
stimuli may, or may not be able to faithfully represent
(even if you were to do the work of creating and
running them all). If you just did it (the sync) then you
would avoid this work and the residual uncertainty.

dick_freebird said:

When you have no care for reset-release race conditions.

Which is never, if you're smart or responsible for outcomes
(such as test development timetable and test repeatability).

.

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It's not never. You have asynchronously reset a flipflop to 0 and it has a 0 on its D input. You have a race between the reset
deassert trying to keep it at 0 and the rising edge of clock trying to set it to 0.

The winner is going to be 0. There is no way that it will somehow flip to 1 in this scenario. The reset to clock setup time only applies
when you are trying to flip its state. You can ignore it when the state doesn't change.

John Eaton