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[SOLVED] Glitches of switched-capacitor circuits

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chandlerbing65nm

chandlerbing65nm

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what are the switched capacitor glitches that can be solved by making a good clock generator.

I have a clock generator made and its application is to test the clocks to a switched capacitor, what are the parameters that i should look for if I'm aiming to solve those glitches using my clock generator.

My clock Generator frequency is 32kHz. what kingd of switched capacitor I can use for this?

Also if you can provide or tell some full research paper regarding my matter, it would be very helpful.
 

The main thing is to have nonoverlapping clock phases such
that the charge is held or shared, but never passed ohmically
across the capacitors (no cross conduction of switches).

There will always be some glitch energy, you use device
sizing to mimize the total and balance the direction of
switching charges for a minimum impact to "information"
charge.
 

Nothing can get rid of the charge injection issue that depends on the impedance on either sides of the switch. A good design is all that can be done. The parameters you should be looking at are
1) charge injection: When the switch is turned off, the charges in the channel leave the channel and flow either side of the switch depending on the impedance seen. This will cause delta-change in the voltage on the capacitor.
2) clock feed through: Due to parasitic gate-drain and gate-source capacitances, the clock feeds through and changes the held voltage on the cap.
 

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