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Simulating Xilinx smpte sdi core

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paulr127

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Hi everyone,

I have generated this core in Xilinx Vivado. It has a demo tb....

Can anyone guide me how to simulate it??Can't figure out what files to compile(design files).


Many thanks
 

Read Chapter9 of the docu mentioned in the above post.

1st and foremost, did you generate the core successfully?

If yes, just right_click inside Vivado on the core top_level file and generate its "example_design".
Vivado will create a new project for you with a test_bench wrapper over the core.
Then open this new project and just "Run Simulation".

Recommended reading : https://www.xilinx.com/support/docu...7-vivado-design-suite-simulation-tutorial.pdf
 
Thanks very much for all your help. This was exactly what I needed

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Hi Paul

thanks for your response. I am able to simulate it but not using the way you described and would be interested to replicate that... When I right click (.......xci) file I don't see the option of generating example design.... Please advise.

Thanks
 

Sorry.....I missed this info.

See Chapter8 of the IP core spec - "No example design is available at the time for the SMPTE SD/HD/3G-SDI 3.0 core"
So ignore the way of generation I mentioned above.

But see Chapter9: "A demonstration test bench is provided with the core which enables you to observe core behavior in a typical scenario. This test be nch is generated together with the core in Vivado Design Suite."
 
BTW Thanks for all your help. I was able to simulate in vivado. What do I need to do if I want to simulate in modelsim/questasim. thanks very much

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The problem is I don't see the log file (it is not there in sim dir simulation.log is empty) and the messages about testing the video formats. Also it is just running one record and I would appreciate your help as to figure out why and how to run all the records. Many thanks
 

What do I need to do if I want to simulate in modelsim/questasim.

The problem is I don't see the log file (it is not there in sim dir simulation.log is empty) and the messages about testing the video formats.

Ans to both Q can be found inside the docu - UG900 (v2016.4) November 30, 2016
 

Thanks very much. BTW what does this expression mean in verilog

v <= # DLY line < first_active-1;
 

This is completely different to the topic you started.
A new thread is needed in this case.

Please read the forum posting rules!
 

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