Need your feed back in my published paper Hybrid NMOS/PMOS capless LDO

Dear All

I recently published this paper "A hybrid NMOS/PMOS low-dropout regulator with fast transient response for SoC applications", We also have an extended edition that is under revision in a prestigious journal. I hope if you can give me your feedback about this research work (Fulltext is available, just send me a private message)
https://ieeexplore.ieee.org/document/8268850/

Best Regards,
Mahmoud

IEEE wants us to pay to look at it, so I expect not much
help may be forthcoming. If you post a link that does not
hide behind their pay wall you might get more support.

Thanks a lot for your clarification
Here a link from researchgate available to download without payments or login account

Here are some thoughts:

- I like the concept but you might find some issues in
the user base, from the presence of the charge pump.
Its frequency may be variable and its spurs objectionable
to wireless and high speed serial "clients" and "neighbors".
You might investigate CP spurs amplitude into different
loads, especially since there is to be no subsequent
filtering ("capless"). Also the magnitude of current spikes
from CP into + and - supplies (along with fundamental
frequency variation (if not clock-mastered) and harmonics
may be of keen interest to your "target market" (people
use LDOs because they expect them to be quiet and/or
simple & compact; are you willing to forego the "quiet"
segment (thinking as a products guy more than a
researcher)?

- Discuss the pros and cons of using the pass transistor
couple to reduce maximum Zout, vs other schemes such
as a Class AB output ("braking NMOS" on the low side).

- The mag / phase plots would benefit by a A=0 and P=180
"cursor" pair, so the phase margin can be seen clearly from
Fig 5's two separate panes - or make the two panes,
light load mag & phase, full load mag & phase.

- ~20-30% overshoots are not good despite that they recover
"quickly" (we could quibble over whether 500nS is "quick"
for 130nm technology, it is hundreds of clock cycles). I
have often had to trade settling time for lesser overshoot /
load step (say, by output filter - nil on a capless LDO by
definition, so no help there). The detail plot of the recovery
seems to indicate "edgy" phase margin (slightly underdamped)
in Fig 6b

- You might discuss the partitioning of Mp, Mn - appears that
in the design, the NMOS always carries more current than
the PMOS. This implies that the FET may be bigger than it
should be, maybe injecting more CP noise as a result. If
the NMOS w/ CP is indeed capable of most or all current,
if you're going to have the CP anyhow, then what is the
value of the PMOS loop at all? Why not just a "ULDO" with
a charge pump instead of a VAUX, why keep the PMOS?

WOW This is the best feedback and it is really helpful, I really appreciate your time.

-- The CP is used to supply only the level shifter which causes ripples at the output, but the ripples less than 1% in the output.
Using CP to supply the level shifter only relaxed the need for high clocking frequency and also the size of caps inside the CP (yet, of course, these ripples may not be good for high-speed circuits)

-- I think yes we should discuss other schemes and I will add it to my literature in the thesis.

-- Regarding phase margin, I added a curve in our extended version for the phase margin while changing load current. The phase margin is improved at higher load currents to ~80 degrees.

-- The phase margin is around 47 degrees at low load current (10 uA). It was a tradeoff I had to face either make it fast (competitive to other designs) or improve phase margin more.
Based on studying other designs we decided to concentrate on the speed as it is our good number of other designs.

-- There are many papers discussed segmentation of pass transistors using two PMOS transistor, in this work we are trying to use another way of segmenting current between two different pass transistors.
If we used NMOS only we will have to use very large size NMOS or use extra stages of the charge pump to increase the gate voltage of the NMOS.
Also, The PMOS is providing another high-speed loop to help the regulator to respond faster to the abrupt changes in the output voltage and also increases the loop gain (so better line/load regulator- static specs)
Whereas the PMOS is off at low currents so that the NMOS pass transistor can carry more current so that the output pole is moved to higher frequencies (2nd dominant frequency at low load current)
that let us make the BW of the LDO higher using smaller compensation cap (700fF).

Nice article.
At section II/A: Two poles at the gate? The dominant and the mirror pole? Mirror pole is not at the gate of MP I think. You didn't mention RHPZ, but not too hard to compensate that.
At section II/B: NMOS can be a native device without threshold voltage, so the max Vout can be higher. I know sometimes it is extra cost, but at 130nm probably not too big, I don't know.
PSRR is Power Supply Rejection. If it is negative that means the rejection is negative and the gain of supply noise is positive, but lot of engineer use negative value for it.
Did you run PVT and Monte Carlo? How much is the offset and Phase Margin variation? I am just curious, probably these are not the main things in a scientific article.

Mahmoud, just a small remark:

I think the abbreviation FVF (flipped voltage follower) should be explained when you use this abbreviation the first time.
Sure, I know it's in the title of paper [5] which appears a few lines below, but anyway ...

BTW: The original FVF paper already turned up a few (3) years earlier - by the same authors, however:

[Ramírez-Angulo’92] J.Ramírez-Angulo, R.G.Carvajal, A.Torralba, J.Galán, A.P.VegaLeal, and J.Tombs :
“The Flipped Voltage Follower: a useful cell for low-voltage low-power circuit design”
Proc. ISCAS’02, vol. 3, pp. 615-618, 2002

frankrose said:

Nice article.
At section II/A: Two poles at the gate? The dominant and the mirror pole? Mirror pole is not at the gate of MP I think. You didn't mention RHPZ, but not too hard to compensate that.
At section II/B: NMOS can be a native device without threshold voltage, so the max Vout can be higher. I know sometimes it is extra cost, but at 130nm probably not too big, I don't know.
PSRR is Power Supply Rejection. If it is negative that means the rejection is negative and the gain of supply noise is positive, but lot of engineer use negative value for it.
Did you run PVT and Monte Carlo? How much is the offset and Phase Margin variation? I am just curious, probably these are not the main things in a scientific article.

Click to expand...

Many thanks for your feedback

Section II/A
this topology has stability problems, especially at light loads, mainly due to the two poles at the gate of the power transistor (MP) and at the output of the LDO.
I mean one at the PMOS gate and one at the output of the LDO.

Section II/B
In this section we were talking generally about NMOS LDO. I knew about native transistors but besides the problem of the fab cost it also has the problem of not stable VTH I think
(the threshold voltage is changeable and more immune to variations)

PSRR: In LDO literature of simulation and measure of PSRR is to take the signal output to the VDD input voltage. (applying ac signal in VDD and measure the gain from the outout to VDD) all papers on LDO work in the same method so the PSRR should be negative.

PVT/Monte Carlo: I think monte carlo is not a big problem in LDO which as a Corner analysis is preferred more. I will run corner analysis and add it to my thesis. After layout the PM is worse donw to 44 degrees making it slower.

- - - Updated - - -

erikl said:

Mahmoud, just a small remark:

I think the abbreviation FVF (flipped voltage follower) should be explained when you use this abbreviation the first time.
Sure, I know it's in the title of paper [5] which appears a few lines below, but anyway ...

BTW: The original FVF paper already turned up a few (3) years earlier - by the same authors, however:

[Ramírez-Angulo’92] J.Ramírez-Angulo, R.G.Carvajal, A.Torralba, J.Galán, A.P.VegaLeal, and J.Tombs :
“The Flipped Voltage Follower: a useful cell for low-voltage low-power circuit design”
Proc. ISCAS’02, vol. 3, pp. 615-618, 2002

Click to expand...

Aha, Very very good point I didn't have this info, I just wanted to refer to a conventional FVF I will add the original paper in my thesis Thank you.
We explained it in the IEEE version this is a preprint version (I don't know if I can share the final version without copyrights problems with IEEE)