Continue to Site

Welcome to EDAboard.com

Welcome to our site! EDAboard.com is an international Electronics Discussion Forum focused on EDA software, circuits, schematics, books, theory, papers, asic, pld, 8051, DSP, Network, RF, Analog Design, PCB, Service Manuals... and a whole lot more! To participate you need to register. Registration is free. Click here to register now.

How to polarise the Deep N-Well (WB) or tap WB in the layout

Status
Not open for further replies.

tisheebird

Member level 5
Joined
Feb 23, 2017
Messages
88
Helped
0
Reputation
0
Reaction score
0
Trophy points
6
Activity points
662
Hello

I have done the layout but need to tap WB or polarise "DNW" so please anyone could tell me how we can do it.?
I need to polarise it to VDD right..?

Please guide me with the steps.
 

You need to connect a VIA from nwell to the appropriate metal you tend to use. to check the correct via if you don't know I advice you to use LVS test.
 

You need to connect a VIA from nwell to the appropriate metal ...

No: From nwell (or any other silicon surface) you need a contact opening (not a via) to metal1 . In ICs, vias are ties between different metal layers only. Simply a naming convention.
 
No: From nwell (or any other silicon surface) you need a contact opening (not a via) to metal1 . In ICs, vias are ties between different metal layers only. Simply a naming convention.

You saved me. I just fixed it in my report thanks to you.

I think it is important to know the naming conventions
Your help is really appreciated
 

Need to check your layout design rules. Some processes with dnwell require some type of termination ring around the edge of the dnwell. It is all dependent on the technology
 

Status
Not open for further replies.

Part and Inventory Search

Welcome to EDABoard.com

Sponsor

Back
Top