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expertengr
Guest
Hello, there are DSP slices in Modren FPGAs. Do they work on single clock cycle ? for example if an FPGA has 220 DSP slices and each can support and can handle the multiplication of 18 x 25, does this means that this operation will be done in single clock cycle by each DSP slice ?
Second question how to assign intentionally a DSP slice in VHDL code. Is it possible to assign intentionally ? Following is an example.
Is this (assignment of DSP slices) done automatically during synthesis and tool optimization or can be done manually in VHDL code ?
Second question how to assign intentionally a DSP slice in VHDL code. Is it possible to assign intentionally ? Following is an example.
Code:
architecture behav of multiply_unsigned is
begin
Res <= A * B;
end behav;
Is this (assignment of DSP slices) done automatically during synthesis and tool optimization or can be done manually in VHDL code ?
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