High-frequency lock-in - analog rectifier VS analog mixer VS digital mixer

Dear electronic friends,

I am designing a multi-channel diode sensor PCB with high-frequency excitation (500 kHz - 10 MHz) and lock-in technique. The diode is excited with a high-frequency bias voltage and the current is measured via TIA. The light ("gate") of the diode modulates the amplitude and phase of diode current with a broad spectral range (DC - 100 kHz).

The design facts in short:
- Adjustable high-frequency excitation of the diode bias voltage: 500 kHz < f_c < 10 MHz
- Broadband diode current to be measured via TIA (amplitude and possibly phase): DC < f_m < 100 kHz
- Transimpedance amplifier (TIA) and gain-stage are both specified for 100 MHz
- ADC converter with max. 50 MSPS
- Opal Kelly XEM7310 FPGA with 200 MHz clock

Question (1) Which lock-in technique is the best for measuring amplitude and phase (for fc=10 MHz)? Analog rectifier, analog mixer or digital mixer?
I have simulated all possible techniques and came to some interesting conclusions:
- The digital lock-in realization resulted in a perfect calculation of the signal amplitude (multiplication with sin and cos of reference frequency, low-pass filters and root-mean square summation), ONLY if the measured signal has a CONSTANT phase shift compared to the reference excitation signal. When the phase changes slowly over time, it will be included in the in the calculated signal amplitude. Is there any clever way to obtain a perfect amplitude that is not affected by phase changes?
- When the modulated signal is rectified and smoothed with a capacitor and resistor, the result looks very good if the time-constant of capacitor and resistor is appropriately tuned (about fc/10). Conveniently, the obtained signal amplitude is NOT affected by temporal changes in the phase between measured signal and reference excitation signal. The disadvantage is that the phase information is completely lost, and a different smoothing capacitor/resistor has to be used for different excitation frequencies.
- A digital lock-in realization is more accurate than an analog one, because one can calculate a perfect sine wife without distortions. But, this requires a very good ADC bandwidth and dynamic range. What is if the ADC sampling frequency is only 5 times larger than the excitation frequency (carrier frequency)? Will it be still more accurate than its analog companion?

Question (2) Excitation better with a DAC generated sine wave or with a sine wave generator (AD9833)?
It seems that the sine wave for the sensor excitation must be perfectly harmonic. Noise near the excitation frequency (carrier frequency) f_c might disturb the modulated signal f_m especially at very low frequencies (because f = f_c + f_m after modulation). That means a DAC with 5-10 samples per period would lead to significant distortions, right? So, I would have to use the AD9833 for high-quality sine wave generation and somehow synchronize it with the FPGA?

Thanks so far!

Your considerations about digital signal processing don't sound substantiated.

E.g.:

Excitation better with a DAC generated sine wave or with a sine wave generator (AD9833)

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AD9833 is a DAC based sine wave generator (DDS). Nyquist law rules. With respective filters, a sampling frequency slightly above double carrier frequency is sufficient to generate or demodulate the signal of interest.

Digital receivers with quadrature demodulation are the preferred solution for a wide range of todays communication applications.

Your considerations about digital signal processing don't sound substantiated.

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Ok, I should be more precisely here: When I simulate low oversampling (fs=2.5*fc), the time-variant phase drift of the measurement signal's carrier frequency shows up in the demodulated amplitude signal.

If the AD9833 would be just a pure DAC (without internal clock or clock multiplication), then the output sine wave would look like a square wave for f=fclk/2, right? Or in other words the amplitude of the third harmonic would be about -10 dB. Similarly, for f=fclk/7 the amplitude of the third harmonic would be about -15 dB. But, this in in contradiction with figure 15 in the datasheet, where a 1.43 MHz sine wave with a 10 MHz clock (f=fclk/7) produces a second harmonic with an incredibly low amplitude of -60 dB. So, it seems that the AD9833 has an internal fast clock or clock multiplier in order to produce smooth sine waves, and the external clock is only for synchronization purposes? However, the datasheet doesn't say anything about an internal clock or clock multiplier... So, how is such an incredibly pure sine wave possible with f=fclk/7 or even f=fclk/2 ??
Can I trust the datasheet or should I better use the more complex AD9106 with fclk=180 MHz?

I agree that a digital lock-in is most accurate variant, but only if the FPGA is capable to process the large amount of data. Is the Opal Kelly XEM7310 FPGA (with 200 MHz clock and 128 I/Os) able to drive 4x ADCs, each with 50 MSPS and 14 parallel bits and able to process the data on-the-fly with 4x digital lock-in implementations on the FPGA (digital multiplications, digital low-pass filtering...)?

How precise would be a simple rectifying diode (plus a capacitor and resistor for smoothing) for amplitude demodulation?

Hi,

... then the output sine wave would look like a square wave for f=fclk/2, right?

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This is off nyqist reqirement. f=fclk/2 will never work.

And if you are that close to nyquist (like fs = 2.5 × f) then you need an (almost) perfect reconstruction filter, else you get a sinewave with amplitude variation. It's not a problem of the DAC, it's a problem of the analog filter.

Or in other words the amplitude of the third harmonic would be about -10 dB. Similarly, for f=fclk/7 the amplitude of the third harmonic would be about -15 dB. But, this in in contradiction with figure 15 in the datasheet, where a 1.43 MHz sine wave with a 10 MHz clock (f=fclk/7) produces a second harmonic with an incredibly low amplitude of -60 dB.

Click to expand...

A perfect reconstruction filter supresses the overtones. But the problem is that you can't build a perfect sin(x)/x reconstruction filter. Neiter analog nor digital.

Klaus

Hi,

Thanks! That makes sense and makes my decision easy. So, I will use the AD9106 that has a sample rate of 180 MHz, followed by a 2nd order 15 MHz low-pass filter. With this I should be able to generate sine waves (200 kHz - 10 MHz) with harmonics below -60 dB.

Do you think that analog I/Q demodulation (with a AD8333) of the carrier frequency is possible with such a quality of a sine wave? I know that for digital I/Q demodulation the quality of the sine wave plays much less of a role. But, for a digital implementation I would need a much higher sample rate (4x 50 MSPS instead of 4x 500 kSPS) and I am not sure whether the FPGA is capable of processing such large data rates (including the digital lock-in demodulation)? If an analog or digital I/Q demodulation is problematic, I could easily demodulate by rectifying with a diode, or better not? I need a good demodulation quality especially for low-frequency signals.

Thanks!

If the AD9833 would be just a pure DAC (without internal clock or clock multiplication), then the output sine wave would look like a square wave for f=fclk/2, right? Or in other words the amplitude of the third harmonic would be about -10 dB. Similarly, for f=fclk/7 the amplitude of the third harmonic would be about -15 dB. But, this in in contradiction with figure 15 in the datasheet, where a 1.43 MHz sine wave with a 10 MHz clock (f=fclk/7) produces a second harmonic with an incredibly low amplitude of -60 dB. So, it seems that the AD9833 has an internal fast clock or clock multiplier in order to produce smooth sine waves, and the external clock is only for synchronization purposes? However, the datasheet doesn't say anything about an internal clock or clock multiplier... So, how is such an incredibly pure sine wave possible with f=fclk/7 or even f=fclk/2 ??

Click to expand...

There's no internal fast clock in AD9833. Did you notice that all datasheet spectral plots range up to MCLK/2? The device has to be operated with an external filter suppressing signal components above the Nyquist frequency. If you are targeting to 10 MHz signal frequency, it's in fact easier to use a DDS chip with higher sampling rate than 25 MHz, because it relaxes the filter requirements.

AD9833 datasheet isn't very clear in this regard, ADI application notes and more recent devices datasheet are discussing things better.

Do you think that analog I/Q demodulation (with a AD8333) of the carrier frequency is possible with such a quality of a sine wave? I know that for digital I/Q demodulation the quality of the sine wave plays much less of a role. But, for a digital implementation I would need a much higher sample rate (4x 50 MSPS instead of 4x 500 kSPS) and I am not sure whether the FPGA is capable of processing such large data rates (including the digital lock-in demodulation)? If an analog or digital I/Q demodulation is problematic, I could easily demodulate by rectifying with a diode, or better not? I need a good demodulation quality especially for low-frequency signals.

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Your considerations are partly inconsistent. Post #1 discussed magnitude and phase measurement, the latter isn't possible with a diode rectifier. The major advantage of synchronous rectification respectively I/Q demodulation is the huge SNR improvement without using selective analog pre-filters.

I don't see how you arrive at 50 MS/s demand for 10 MHz signal bandwidth. But it's surely no problem for any recent FPGA. Analog demodulation mainly suffers from mixer linearity and SNR, high performance spectrum analyzers are using high level mixers (= square wave like carrier) and pre selection filters to cut potentially aliasing components in input signal. For your frequency range of interest a pure digital receiver solution is preferred and superior in performance.

Thanks for the comments!

AD9833 datasheet isn't very clear in this regard, ADI application notes and more recent devices datasheet are discussing things better.

Click to expand...

Then, I will use the AD9106 with 180 MSPS together with a 2nd order LPF with fc=20 MHz...

I don't see how you arrive at 50 MS/s demand for 10 MHz signal bandwidth. But it's surely no problem for any recent FPGA. Analog demodulation mainly suffers from mixer linearity and SNR, high performance spectrum analyzers are using high level mixers (= square wave like carrier) and pre selection filters to cut potentially aliasing components in input signal. For your frequency range of interest a pure digital receiver solution is preferred and superior in performance

Click to expand...

Following Nyqist, a sample rate of 25 MS/s would be sufficient for a 10 Mhz signal bandwidth. But, I thought it might be better to oversample 5x the carrier frequency? In the extreme case, the sensor excitation frequency (=carrier frequency) will be 10 Mhz.

The critical point is that I need to measure the sensor signal (=modulation signal) down to very low ferquencies (0.01 Hz - 100 kHz). In order to detect an 0.01 Hz amplitude modulation of a 10 MHz carrier signal (fmix=10.00000001 MHz), I would need an excellent reprensentation of the amplitude, right? That is why I thought it might be necessary to oversample with 50 MS/s. What do you think?

Would you recommend a standard ADC converter such as the AD9649 or LCT1750, or an IF receiver such as the AD6655?

Thanks again!

Which of the following 3 solution is the prefered one to generate an amplitude modulated carrier frequency?

1) Waveform / function generator chip AD9102 / AD9106 (180 MHz) + single-ended buffer + low pass filter + VGA (for programmable amplitude: 10 mV ... 1 V) + bias tee (for DC component) + buffer
2) High-speed DAC AD9707 (175 MSPS, 14 parallel bits) + single-ended buffer + low pass filter + buffer
3) Dual channel laboratory waveform generator (Agilent or HP or...) + coaxial frequency mixer with coaxial output to board + on-board bias tee (for DC component) + buffer ... + sync from waveform generator to the on-board FPGA (for the digital lock-in mixing)

I see the following points:
1) Pro: Few FPGA I/Os needed. Contra: A lot of additional components needed, elaborative programming
2) Pro: Fewer components needed? DC + amplitude modulated carrier frequency can be directly programmed? Contra: Maybe jitter problems, maybe stressing the FPGA bandwidth, a lot of I/Os needed
3) Pro: Pure sine waves, fast design, only one I/O needed for synchronization. Contra: No on-board solution, synchronization of wave generator with FPGA maybe not ideal for the digital lock-in mixing on the FPGA? Maybe PLL needed?

Did I forget any points?