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How to use fpga external memory, steps I already did, questions about them, and how to

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albert1905

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How to use fpga external memory,steps I already did, questions about them, and how to

first I will mention that I read abut still couldn't fully understand :"external memory interface handbook volume 2", and the questions are things that I'm still struggling to understand and need your help.

Im using MAX10 FPGA , quartus 2 and modelsim altera.

Im trying to instantiate sdram controller to my project so Im first learning how to do it, by opening a new clean project.

So, those are the steps I did, and the questions I have about them:

1.ip extraction:
from "ip catalog" I extracted "DDR2 SDRAM controller with uniphy".

2.atttaching files:
From the files that were extracted I took the the project the qip file, which attached all the files.

Q:Do I need all of those files? files like:"sdram_interface_s0.v", "sdram_interface_c0.v","alt_mem_ddrx_input_if. v" .
And Ill be happy to know what are all of those files? are they the "Inside" of the controller ?? and all I have to deal with is :"Sdram_interface.v" file??

3.pin assignments:
I used the tcl script that I got from the extracted ip files.

Q: Do I need anymore assignments to do?

4.Instantiating the module: I instantiate this way:

Code:
    sdram_interface(
    .pll_ref_clk(clk), // in pll_ref_clk.clk
    .global_reset_n(), // in global_reset.reset_n
    .soft_reset_n(), // in soft_reset.reset_n
    .afi_clk(clk), // afi_clk.clk
    .afi_half_clk(), // afi_half_clk.clk
    .afi_reset_n(), // afi_reset.reset_n
    .afi_reset_export_n(), // afi_reset_export.reset_n
    .mem_a(mema), // out memory.mem_a
    .mem_ba(memba), // out .mem_ba
    .mem_ck(mem_clk), // .mem_ck
    .mem_ck_n(), // .mem_ck_n
    .mem_cke(mem_cke), // out .mem_cke
    .mem_cs_n(), // .mem_cs_n
    .mem_dm(), // .mem_dm
    .mem_ras_n(), // .mem_ras_n
    .mem_cas_n(), // .mem_cas_n
    .mem_we_n(), // .mem_we_n
    .mem_dq(), // .mem_dq
    .mem_dqs(), // .mem_dqs
    .mem_dqs_n(), // .mem_dqs_n
    .mem_odt(), // .mem_odt
    .avl_ready(avl_ready), // avl.waitrequest_n
    .avl_burstbegin(avl_burstbegin), // in .beginbursttransfer
    .avl_addr(avl_addr), // in .address
    .avl_rdata_valid(avl_rdata_valid), // out .readdatavalid
    .avl_rdata(avl_rdata), // out .readdata
    .avl_wdata(), // in .writedata
    .avl_be(), // in .byteenable
    .avl_read_req(avl_burstbegin), // in .read
    .avl_write_req(1'b0), // in .write
    .avl_size(2'b10), // in .burstcount
    .local_init_done(), // status.local_init_done
    .local_cal_success(), // .local_cal_success
    .local_cal_fail() // .local_cal_fail
    );

Im still trying to learn what each port do, so I did only the one I know and they are important.


5.wrote to the memory: I wrote to the memory using de control panel ,and I want to check, and see if I can do a read transaction.

Q: I dont really know how to do that.. I know that I need to programm my fpga, but Im affraid that my pin assighnments are not enough, even then, how can I check if the data that was read is correct ?
What am I missing??!!?
Im feeling like I missing a big piece here, and I'll be happy for your help.

Thanks a lot!!!
 

Re: How to use fpga external memory,steps I already did, questions about them, and ho

Normally these ip blocks need a controller to drive them. A lot of the examples and tutorials provided by vendors they tend to use a soft/hard cpu which runs an executable that does the talking to the sdram fpga block.

If you want to get into the weeds ask yourself what bus functional model do you have to drive the sd ram to test your read/writes.

Does the word avalon sound familiar?
 

Re: How to use fpga external memory,steps I already did, questions about them, and ho

Yes it does sounds familiar, I used "DDR2 SDRAM controller with UniPHY", and I thought that the avalon is inside this ip unit.
That's why in the interface i have those pin:
.avl_ready(avl_ready), // avl.waitrequest_n
.avl_burstbegin(avl_burstbegin), // in .beginbursttransfer
.avl_addr(avl_addr), // in .address
.avl_rdata_valid(avl_rdata_valid), // out .readdatavalid
.avl_rdata(avl_rdata), // out .readdata
.avl_wdata(), // in .writedata
.avl_be(), // in .byteenable
.avl_read_req(avl_burstbegin), // in .read
.avl_write_req(1'b0), // in .write
.avl_size(2'b10), // in .burstcount

Or Im missing something!??!

Thanks for your help.
 

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