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Where did the - 0.7 V from the graph came from? (Diode Clampers Circuit)

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Jayce

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I am currently studying how Diode Clampers works. (Sorry for the newbie question.)

0.7.png

Regarding the picture above. On the result waveform after applying clampling / shifting techniques, I am wondering where did the -0.7 V on the graph came from?

On the negative alternation / half-cycle, the Vp(out) is equal to 0 V as there is no current flowing through the load resistor.
On the positive alternation, the Vp(out) is equal to 2 Vp(in) - 0.7 V through applying KVL : V(in) + V(in) - 0.7 - Vp(out).

As the result, the AC waveform shifted upwards. The Vp(in) - 0.7 V on the graph signifies the new / assumed / considered origin to show that it shifted upwards. I don't know why the -0.7 V is labeled on the peak of the negative alternation, wherein the V(out) is 0 V, hence why it is on the 0 / origin line.

Again, sorry for the newbie question but I will appreciate any help. Thank you.
 

Your schematic is the Villard cell. The diode and capacitor pair create a charge pump which is the basis for voltage multipliers. The capacitor charges through the diode in one direction. Then it discharges (adding the supply voltage) through the load. So you get double the voltage.

Briefly the load receives -.7V while the supply waveform goes negative, and that is due to diode clamping action.
 

Your schematic is the Villard cell. The diode and capacitor pair create a charge pump which is the basis for voltage multipliers. The capacitor charges through the diode in one direction. Then it discharges (adding the supply voltage) through the load. So you get double the voltage.

Briefly the load receives -.7V while the supply waveform goes negative, and that is due to diode clamping action.

I got confused with analyzing circuits when it is assumed to be in ideal or practical model. On ideal model, they set the diode as a short component when it is in forward bias, so there will be no current flowing through the load resistor. But on practical model (where voltage drop is considered), when the diode is in forward bias, the load resistor will have the same voltage as the diode because it is connected in parallel.

Wherein, Vo + 0.7 = 0; So Vo = 0.7, hence the -0.7 V on the graph?

Did I get that right? Thank you! I appreciate the answer. :)
 

Right, you've got it (I think). The Villard cell can have various supply waveforms: True AC, DC pulses, inverted DC pulses, etc. And different arrangements of Villard stages (and half-wave power supplies). You can see videos of voltage doublers/ triplers/ quadruplers, on
my Youtube channel 'patientbrad', using my homebrew animated simulator.

As for me I like to watch simulations of this type of voltage multiplier. They defy logic as they appear to produce 'something-for-nothing'. Falstad's simulator is animated and interactive. Easy to use. Free to download at:

www.falstad.com/circuit
 

The voltage across a silicon diode is the threshold voltage = 0.7 volt. So this is the maximum voltage that you can get across it . This clamps the voltage value.
 

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