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Default values of wire and reg in Verilog

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sai_shashi

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Hi All,

I know that the default values of wire and reg in verilog are z and x respectively.

can someone tell me why it is so?

Thanks
shashi
 

Wires typically are used for 'connectivity'. Unconnected? z.
Regs typically are used for 'storage'. No value stored? x.
 

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