doubt on this simple verilog pipeling

// Code your design here
module data_sampling_doubt1 (
  input clk,
  input rst,
  input [3:0] data_in,
  input vld,
  input [1:0] opcode,
  output reg [3:0] data_out1,
  output reg [3:0] data_out2
);
  
  reg [3:0] data_temp;
  

  
  always@(posedge clk)
  begin
    if(rst)
      	data_out1 <= 0;
  	else if(vld)
    	case(opcode)
          
      		2'b11: data_out1 <= data_in;
      		default: data_out1 <= 'hF;
    	  
    	endcase
    else
      	data_out1 <= 'hE;
  end
  
  // pipelining the input port data into a data_temp register//
    always@(posedge clk) begin
    if(rst)
      data_temp <= 0;
    else
      data_temp <= data_in;
  end 
  always@(posedge clk)
  begin
    if(rst)
      	data_out2 <= 0;
  	else if(vld)
    	case(opcode)
          
      		2'b11: data_out2 <=  data_temp;
      		default: data_out2 <= 'hF;
    	  
    	endcase
    else
      	data_out1 <= 'hE;
  end
endmodule

// Code your testbench here
// or browse Examples
module test1();
  
   reg clk;
  reg rst;
  reg [3:0] data_in;
  reg vld;
  reg [1:0] opcode;
  wire [3:0] data_out1;
  wire [3:0] data_out2;
  
 data_sampling_doubt1 dut(
  clk,
  rst,
  data_in,
  vld,
  opcode,
  data_out1,
  data_out2
 );
  
  initial begin
    $dumpfile("dump1.vcd");
    $dumpvars;
    
    rst =1;
    data_in = 0;
    vld = 0;
    opcode = 0;
    #100 rst =0;
    #50;
    data_in = 'hb;
    vld = 1;
    opcode = 'b11;
    #20;
    vld = 0;
    opcode = 0;
    data_in = 'hc;
    #20;
    vld = 1;
    opcode = 0;
    data_in = 'hd;
        #20;
    vld = 0;
    opcode = 0;
    data_in = 'h0;
    #200;
    $finish;
  end
  
  initial
    clk =0;
  always #10 clk = ~ clk;
endmodule