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Synopsys Design Compiler - Ungroup Synthesized Designs

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mahdi.nazemi

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I have a large multi-input multi-output design where each primary output is written in terms of primary inputs. Because the design is so large, DC is unable to synthesize the circuit. A straightforward solution is to synthesize each output individually and later, synthesize the bigger design by instantiating these smaller modules. However, I think there is a lot of room for optimization because all output functions share the exact same inputs.

Does ungrouping different designs optimize mostly around the boundaries or will optimize the whole design regardless of whether each smaller module has been synthesized before or not? If it optimizes the design as a whole, is there an advantage to synthesizing smaller modules first?

In other words, I like to use a divide and conquer method that synthesizes smaller modules first, but takes advantage of the fact that small modules share the same inputs and optimize around boundaries. Is there a DC command that can achieve this?
 

mahdi.nazemi said:
I have a large multi-input multi-output design where each primary output is written in terms of primary inputs. Because the design is so large, DC is unable to synthesize the circuit. A straightforward solution is to synthesize each output individually and later, synthesize the bigger design by instantiating these smaller modules. However, I think there is a lot of room for optimization because all output functions share the exact same inputs.

Does ungrouping different designs optimize mostly around the boundaries or will optimize the whole design regardless of whether each smaller module has been synthesized before or not? If it optimizes the design as a whole, is there an advantage to synthesizing smaller modules first?

In other words, I like to use a divide and conquer method that synthesizes smaller modules first, but takes advantage of the fact that small modules share the same inputs and optimize around boundaries. Is there a DC command that can achieve this?
Click to expand...

There is no direct command to achieve all of that in one go. The tools are not prepared to handle synthetic circuits like the one you describe. It's up to you to work around it.
 

ThisIsNotSam said:
There is no direct command to achieve all of that in one go. The tools are not prepared to handle synthetic circuits like the one you describe. It's up to you to work around it.
Click to expand...

Do you mind sharing some pointers to how I can work around it? Is there a set of commands I can use to solve this problem?
 

mahdi.nazemi said:
Do you mind sharing some pointers to how I can work around it? Is there a set of commands I can use to solve this problem?
Click to expand...

There isn't. You can try to split the circuit by logic cones and then merge, even so I am not sure what you will get in the end.
 

mahdi.nazemi said:
I have a large multi-input multi-output design where each primary output is written in terms of primary inputs. Because the design is so large, DC is unable to synthesize the circuit. A straightforward solution is to synthesize each output individually and later, synthesize the bigger design by instantiating these smaller modules. However, I think there is a lot of room for optimization because all output functions share the exact same inputs.

Does ungrouping different designs optimize mostly around the boundaries or will optimize the whole design regardless of whether each smaller module has been synthesized before or not? If it optimizes the design as a whole, is there an advantage to synthesizing smaller modules first?

In other words, I like to use a divide and conquer method that synthesizes smaller modules first, but takes advantage of the fact that small modules share the same inputs and optimize around boundaries. Is there a DC command that can achieve this?
Click to expand...

Use bottom-up approach . it will certainly help you.
 

mahdi.nazemi said:
Because the design is so large, DC is unable to synthesize the circuit.
Click to expand...

How large ?? What did the tool say when it could not synthesize ?

The best way for you is to do the bottom-up synthesis flow. It means that, you need to do couple of time of synthesis.
Firstly, do it on lower hierarchical blocks.
The last time, you read all lower level block netlist and synthesis for the top level.

As to ungroup, please do several options, and choose the best one fit your requirement.
We can do some estimation, but it is waste of time when only talking without any eveident.
Ungroup command result also depended on designs by designs.
 

yes the main question is how large is the design. most tools are now a days equipped with larger capacity.
Personally IMO top down flows generate better results always over bottom-up.

Ungroup is one of the most common opt techniques in synthesis but be carefull thsi has implications on EC and also in the long run if you hit ECO's

NOt sure why others say that there are no tools to do the auto partitioning - Mentor, Synopsys and Cadence all these have some at RTL level and some primarily at the netlist/gate level.
 

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