Continue to Site

Welcome to EDAboard.com

Welcome to our site! EDAboard.com is an international Electronics Discussion Forum focused on EDA software, circuits, schematics, books, theory, papers, asic, pld, 8051, DSP, Network, RF, Analog Design, PCB, Service Manuals... and a whole lot more! To participate you need to register. Registration is free. Click here to register now.

Register Log in

Cascode transistor bias connection

Status
Not open for further replies.
C

circuitking

Full Member level 5
Joined
Jan 8, 2018
Messages
291
Helped
1
Reputation
2
Reaction score
1
Trophy points
18
Activity points
2,503
Hi

I would like to know which is the best way to connect cascode transistor while biasing and why. I confused between two ways of connections shown in attachment

cascode.JPG

Thanks
 

The right top transistor is not a cascode just a diode connected device. You can't use that as a cascode...circuitking.
 

When you want it to work as amplifier, while biasing left top transistor we bias it in such a way that it is in saturation.In figure (b) we are directly having it in saturation because of diode connection.May be could you explain when to use fig(a) and fig(b), advantages and disadvantages.
 

We use cascode to shield the bottom transistor from drain voltage variation, and it produces high output impedance. And cascoding has high frequency advantege also, it eliminates the Miller effect and extend the bandwidth of single common-source amplifier. This is on figure (a).
On the right, figure (b) the diode doesn't shield bottom transistor from drain voltage variation, so it is not a cascode just a saturating device in series with the drain. And can't prevent Miller effect either. That is not a cascode, don't call it cascode. It doesn't have any advantage. It has got a disadvantage that limits the output voltage swing.
 

With connecting the top drain to VDD, neither of the circuits makes a reasonable cascode configuration. Actually it has no input or output.

If you expect a verbose explanation of circuit pro and cons, we can expect at least a halfway considered question.
 

FvM said:
With connecting the top drain to VDD, neither of the circuits makes a reasonable cascode configuration.
Click to expand...

I see. What is the appropriate DC value that top drain needs to be connected to. is it more that more than the sum of overdrive voltage of CS and CG transistors?
 

Often you can't get the voltage you really would like
due to headroom, amd have to compromise to best
practical effect.

You would prefer the "master" FET to be in saturation
region at max current / max Vgs and so gate for the
"guard" should be at least 2*Vgs(op). But too high and
the "guard" may fall out of saturation instead.

Guard Vgs might also be set to enforce a matched Vds
to some other device related to the "guard" (say, a
common source gain stage preceding it, or "diode load"
devices, etc.

Since we know nothing about context, it's on you to
cut and try, steal and beg ideas (and here we are).
But there could be more of the other three, first.
 

Status
Not open for further replies.

Similar threads

Part and Inventory Search

Welcome to EDABoard.com

Sponsor

Back
Top