DC voltage and ac signal of the bulk in bulk driven transistor

Hi

I want to ask can i apply a low voltage to the bulk as compare to the source in bulk driven PMOS transistors because in bulk driven PMOS the inputs are applied to the bulk i.e DC +ac signal. The DC common mode voltage is low 100mV. Source at 300mV but the problem is the parasitic diodes are getting forward bias at this voltage.

If I apply high voltage at the bulk let say 400mV i.e. greater than the source which is 300mV to make the parasitic diodes reverse biased.then the theory of low voltage operation for bulk driven is not valid because applying 0.4 at bulk or at the gate are the same. In both cases we have to apply 0.4V then how this bulk driven is said to be used for low voltage

ICdesignerbeginner said:

Source at 300mV but the problem is the parasitic diodes are getting forward bias at this voltage.

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For silicon, at 300mV diode forward voltage the forward current will be at the order of picoAmpères.

ICdesignerbeginner said:

If I apply high voltage at the bulk let say 400mV i.e. greater than the source which is 300mV to make the parasitic diodes reverse biased.then the theory of low voltage operation for bulk driven is not valid because applying 0.4 at bulk or at the gate are the same.

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For me, your biasing isn't clear. I think it would be better if you show a schematic with node voltages (with + or - sign, if appropriate), referring to a given reference node.

ICdesignerbeginner said:

In both cases we have to apply 0.4V then how this bulk driven is said to be used for low voltage

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Who said this, and where?

I think if source of PMOS is 300mv then we have to aaply greater than 0.3 volts to keep the parasitic diode reverse bias. If its bulk driven 0.4 has to be applied at bulk.
Normally gate voltage is kept greater then vth which is 0.4v or greater
If 0.4 is applied with gate driven and same 0.4v is applied for bulk driven then in both cases 0.4v is applied then how bulk driven is said to be used for low voltage?

Hi

The question which I want to clearify is about bulk driven technique. Input signal (AC +DC) is applied at the bulk of the input transistors. What input DC common mode voltage I can apply? When I am applying a DC voltage lets say 200mV and voltage at the source of input transistors(PMOS) has a DC voltage lets 380mV (which I am getting in my circuit). It means the internal parasitic diodes between the bulk and source will get forward bias which should not be the case.

To make the parasitic diodes between bulk and source reverse biased, the bulk DC voltage applied should be greater than 380mVs.This means I have to apply 380mV at every cost in case of bulk driven I have to apply at the bulk and if we use gate driven we have to apply it at the gate because threshold voltage is somewhere around 0.4V. Then why we say bulk driven is used for low supply as in both cases( gate driven and bulk driven) a DC voltage input of greater than 380mV is applied?

Secondly in papers its mentioned bulk driven reduces the threshold voltage from signal path . Is it because at the bulk we dont need threshhold voltage for channel formation?

ICdesignerbeginner said:

Secondly in papers its mentioned bulk driven reduces the threshold voltage from signal path . Is it because at the bulk we dont need threshhold voltage for channel formation?

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Why don't you simply simulate this relationship? The result will answer your question(s).

Yes, I have simulated but I cant understand what DC voltage do I have to apply at the bulk right now in the attached schematic I have just applied 100mV ac signal at the bulk no DC voltage still its working.



I am operating these transistors in subthreshold region

ICdesignerbeginner said:

... I have just applied 100mV ac signal at the bulk no DC voltage still its working.

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Wrong: you have Vgs(M0,M1)=-284.6mV

Why shouldn't it still work? 100mV ac signal shouldn't be too big a problem for bulk control at this DC bias, apart from some commensurable leakage current during the negative ac peaks. But what for? What do you intend with this bulk control? What's the purpose?

I think you only earn disadvantages compared to gate control: lower input impedance (junction instead of dielectric isolation, and much higher input capacitance), and the need for isolated MOSFETs in their own n-well (PMOS) resp. p-well in n-well (NMOS), if used.

I mean to say I havent applied a DC common mode voltage at the bulk on input pairs. Normally in PMOS the bulks are connected to VDD here in this case I am applying only AC at the bulks. How can I verify that the VTH is removed from signal path?

I am using bulk driven to reduce the supply voltage and secondly the linearity is better for bulk driven as compare to gate driven. I am designing a low frequency OTA.

ICdesignerbeginner said:

I mean to say I havent applied a DC common mode voltage at the bulk on input pairs. Normally in PMOS the bulks are connected to VDD here in this case I am applying only AC at the bulks.

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Wrong: the ac voltage sources V1 & V2 represent DC short circuits to GND, you could have verified this if you had checked its backannotated DC voltages: 0 resp. -0V .

ICdesignerbeginner said:

How can I verify that the VTH is removed from signal path?

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It is not, s. above!

ICdesignerbeginner said:

I am using bulk driven to reduce the supply voltage and secondly the linearity is better for bulk driven as compare to gate driven.

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I doubt both - I guess you must have misunderstood some paper - which you didn't reveal to us.