discover93
Newbie level 5
Hi everyone. Trying to simulate Static cmos full adder, It seems that something is wrong with the gate. I will appreciate it if you help me find it.
Here is the code:
Also I would like to know which full adders(in other logics) has the same noise margin as static cmos. Because the rest of my circuit is in static cmos.
Thanks.
Here is the code:
Code:
# FA
.option post accurate nomod
.include ./22nm_lp.pm.txt
.include ./inverter.sp
*carry
M1 2 b 1 1 pmos l=22n w=33n
M2 coutb a 2 2 pmos l=22n w=33n
M3 3 a 1 1 pmos l=22n w=33n
M4 3 b 1 1 pmos l=22n w=33n
M5 coutb c 3 3 pmos l=22n w=33n
M6 coutb a 4 4 nmos l=22n w=33n
M7 4 b 0 0 nmos l=22n w=33n
M8 coutb c 5 5 nmos l=22n w=33n
M9 5 a 0 0 nmos l=22n w=33n
M10 5 b 0 0 nmos l=22n w=33n
*sum
X_invertera 1 a aa inverter
X_inverterb 1 b bb inverter
X_inverterc 1 c cc inverter
Ms1 2 cc 1 1 pmos l=22n w=33n
Ms2 3 b 4 4 pmos l=22n w=33n
Ms3 3 bb 2 2 pmos l=22n w=33n
Ms4 outb a 3 3 pmos l=22n w=33n
Ms5 4 c 1 1 pmos l=22n w=33n
Ms6 5 b 2 2 pmos l=22n w=33n
Ms7 5 bb 4 4 pmos l=22n w=33n
Ms8 outb aa 5 5 pmos l=22n w=33n
Ms9 outb a 6 6 nmos l=22n w=33n
Ms10 6 b 7 7 nmos l=22n w=33n
Ms11 6 bb 9 9 nmos l=22n w=33n
Ms12 7 c 0 0 nmos l=22n w=33n
Ms13 outb aa 8 8 nmos l=22n w=33n
Ms14 8 b 9 9 nmos l=22n w=33n
Ms15 8 bb 7 7 nmos l=22n w=33n
Ms16 9 cc 0 0 nmos l=22n w=33n
X_invertercout 1 coutb cout inverter
X_inverterout 1 outb out inverter
vdd 1 0 dc 0.95V
vina a 0 pulse 0 0.95 0 200p 200p 7800p 16000p
vinc c 0 pulse 0 0.95 0 200p 200p 3800p 8000p
vinb b 0 pulse 0 0.95 0 200p 200p 1800p 4000p
.tran 2000p 16000p
.endAlso I would like to know which full adders(in other logics) has the same noise margin as static cmos. Because the rest of my circuit is in static cmos.
Thanks.