How to "ARCTAN" Function in VHDL

1. How to "ARCTAN" Function in VHDL

I am a student and doing my final project. I need to find θ = atan (Y/X) in VHDL.
in this they give different Math functions. Can any one tell me how can I write a code to find the phase value θ.

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2. Re: How to "ARCTAN" Function in VHDL

Hi,

I don´t know the VHDL solution.

Often with atan one like to get the direction of a vector. 0...360°.
But atan repeats every 180°. You may need additional logic to get full 360° information.

Klaus

3. Re: How to "ARCTAN" Function in VHDL

That package you posted is part of the VHDL standard, but it is not synthesisable (ie, you cannot use it on a chip). You can use it to calculate constants/generics in your VHDL design at elaboration time.
For trigonometric functions, most people look into using a CORDIC function, or build a look up table (you can use math_real to calculate this).

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4. Re: How to "ARCTAN" Function in VHDL

Originally Posted by Krishna_k
I am a student and doing my final project. I need to find θ = atan (Y/X) in VHDL.
in this they give different Math functions. Can any one tell me how can I write a code to find the phase value θ.
You have to write your own 'code' to calculate atan(x) value. Another possibility is to use vendor specific IP core:
https://www.altera.com/en_US/pdfs/li...altfp_mfug.pdf
You may want to convert signed/unsigned value into ieee754 format, calculate atan(x) and then again do a conversion from ieee754 into signed/unsigned.

5. Re: How to "ARCTAN" Function in VHDL

Thanks all for replying

I try to apply your given solutions but problem accrue in look up table as well as in CORDIC is there is less space remaning in FPGA board. So I have to cancle that idea.
If am no wrong I can write a code using Taylor Series which is
arctan(x)=x-x^3/3+x^5/5-x^7/7+ ...

I am trying to write code but error accrue here, below code is given. It says that Type of aout is incompatible with type of 'conversion to unsigned'

```Code C - [expand]1
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library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.numeric_std.all;

entity atan_try is
port(
xin : in std_logic_vector(31 downto 0);
aout : out std_logic_vector(31 downto 0)
);
end atan_try;

architecture Behavioral of atan_try is

begin

aout <= unsigned (signed(xin) - ((signed(xin)*signed(xin)*signed(xin))/3) + ((signed(xin)*signed(xin)*signed(xin)*signed(xin)*signed(xin))/5) - ((signed(xin)*signed(xin)*signed(xin)*signed(xin)*signed(xin)*signed(xin)*signed(xin))/7));

end Behavioral;```

6. Re: How to "ARCTAN" Function in VHDL

Without looking into the internal calc....
Yes, because aout is of type std_logic_vector and you are type casting the entire calc to unsigned.

Try this:
aout <= std_logic_vector( unsigned (signed(xin) - ((signed(xin)*signed(xin)*signed(xin))/3) + ((signed(xin)*signed(xin)*signed(xin)*signed(xin)* signed(xin))/5) - ((signed(xin)*signed(xin)*signed(xin)*signed(xin)* signed(xin)*signed(xin)*signed(xin))/7)) );

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7. Re: How to "ARCTAN" Function in VHDL

Besides using incompatible types, there are problems with data width and result scaling. It's also inappropriate to use division operations for the Fourier parameter scaling.

The result of a simple chained multiply of 7 32-bit numbers has a width of 7*32 bits. You'll define a fixed point interpretation of the 32 bit input number and get a 32 bit result by respective rounding and truncation.

Division should be replaced by a multiply with fixed point constant.

Instead of chained asynchronous multiply, you better perform sequential multiply with x² in a clocked process.

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