Continue to Site

Welcome to EDAboard.com

Welcome to our site! EDAboard.com is an international Electronics Discussion Forum focused on EDA software, circuits, schematics, books, theory, papers, asic, pld, 8051, DSP, Network, RF, Analog Design, PCB, Service Manuals... and a whole lot more! To participate you need to register. Registration is free. Click here to register now.

Shift register bitwidth issue

Status
Not open for further replies.

promach

Advanced Member level 4
Joined
Feb 22, 2016
Messages
1,199
Helped
2
Reputation
4
Reaction score
5
Trophy points
1,318
Activity points
11,636
Why do RD_DATA and wDataShift need bitwidth of "[(C_DEPTH+1)*C_WIDTH-1:0]" in the following "shift register" module ?



Code Verilog - [expand]
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
// ----------------------------------------------------------------------
// Copyright (c) 2016, The Regents of the University of California All
// rights reserved.
// 
// Redistribution and use in source and binary forms, with or without
// modification, are permitted provided that the following conditions are
// met:
// 
//     * Redistributions of source code must retain the above copyright
//       notice, this list of conditions and the following disclaimer.
// 
//     * Redistributions in binary form must reproduce the above
//       copyright notice, this list of conditions and the following
//       disclaimer in the documentation and/or other materials provided
//       with the distribution.
// 
//     * Neither the name of The Regents of the University of California
//       nor the names of its contributors may be used to endorse or
//       promote products derived from this software without specific
//       prior written permission.
// 
// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL REGENTS OF THE
// UNIVERSITY OF CALIFORNIA BE LIABLE FOR ANY DIRECT, INDIRECT,
// INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
// BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
// OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
// ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR
// TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE
// USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH
// DAMAGE.
// ----------------------------------------------------------------------
/*
 Filename: shiftreg.v
 Version: 1.0
 Verilog Standard: Verilog-2001
 
 Description: A simple parameterized shift register. 
 
 Notes: Any modifications to this file should meet the conditions set
 forth in the "Trellis Style Guide"
 
 Author: Dustin Richmond (@darichmond) 
 Co-Authors:
 */
`timescale 1ns/1ns
module shiftreg
    #(parameter C_DEPTH=10,
      parameter C_WIDTH=32,
      parameter C_VALUE=0
      )
    (input                            CLK,
     input                            RST_IN,
     input [C_WIDTH-1:0]              WR_DATA,
     output [(C_DEPTH+1)*C_WIDTH-1:0] RD_DATA);
 
    // Start Flag Shift Register. Data enables are derived from the 
    // taps on this shift register.
 
    wire [(C_DEPTH+1)*C_WIDTH-1:0]    wDataShift;
    reg [C_WIDTH-1:0]                 rDataShift[C_DEPTH:0];
 
    assign wDataShift[(C_WIDTH*0)+:C_WIDTH] = WR_DATA;
    always @(posedge CLK) begin
        rDataShift[0] <= WR_DATA;
    end
    
    genvar                                     i;
    generate
        for (i = 1 ; i <= C_DEPTH; i = i + 1) begin : gen_sr_registers
            assign wDataShift[(C_WIDTH*i)+:C_WIDTH] = rDataShift[i-1];
            always @(posedge CLK) begin
                if(RST_IN)
                    rDataShift[i] <= C_VALUE;
                else
                    rDataShift[i] <= rDataShift[i-1];
            end
        end
    endgenerate
    assign RD_DATA = wDataShift;
    
endmodule

 

Did you understand the purpose of the module at all? Apparently the module exposes all shift register taps.
 
exposes all shift register taps.

I am sorry, but I do not understand the purpose of the module.

I could not comprehend why the author needs such bitwidth for RD_DATA and wDataShift
 

I don't understand the word "issue" in the thread title.

You don't use the code for a specific purpose, you neither can't imagine a possible purpose, why bother with it at all?
 

I am sorry, but I do not understand the purpose of the module.

I could not comprehend why the author needs such bitwidth for RD_DATA and wDataShift

They don't they just decided to expose all the shift register taps.

The purpose of the module is clearly stated in the header (did you read it)
Code:
Description: A simple parameterized shift register.

- - - Updated - - -

Or perhaps you are making a case for the poorly written code that does something different than what is inferred by the parameters.

Code:
parameter C_DEPTH=10,
parameter C_WIDTH=32,
That implies the shift register has 10 pipeline stages and is 32-bits wide, i.e. 10*32 = 320 FFs e.g. output [319:0] RD_DATA;

The output (and the shift register definitions) imply the depth is 11.
Code:
output [(C_DEPTH+1)*C_WIDTH-1:0] RD_DATA);
((10+1)*32)-1 = 351

I'm not overly impressed by the code you've been getting from "The Regents of the University of California". This particular example is really bad IMO.
 
Last edited:
// Start Flag Shift Register. Data enables are derived from the
// taps on this shift register.

Could anyone elaborate on the comments ?
 

It has already been told to you by FVM on #2.

sr.jpg

Q1, Q2, Q3, Q4 are called the shift-reg taps. So wrt your query, Q1 is one enable, Q2 is another enable, and so on.

Note: I didn't look into the RTL you posted in #1.
 

Status
Not open for further replies.

Similar threads

Part and Inventory Search

Welcome to EDABoard.com

Sponsor

Back
Top