promach
Advanced Member level 4
For https://github.com/KastnerRG/riffa/blob/master/fpga/riffa_hdl/tx_port_channel_gate_128.v#L95-L107 , are there any reasons to use one clocked process + one combinatorial process ? Will a single clocked process work less better in real hardware implementation ?
Code Verilog - [expand] 1 2 3 4 5 6 7 8 9 10 11 12 13 always @ (posedge CHNL_CLK) begin rChnlTx <= #1 (RST ? 1'd0 : _rChnlTx); rChnlLast <= #1 _rChnlLast; rChnlLen <= #1 _rChnlLen; rChnlOff <= #1 _rChnlOff; end always @ (*) begin _rChnlTx = CHNL_TX; _rChnlLast = CHNL_TX_LAST; _rChnlLen = CHNL_TX_LEN; _rChnlOff = CHNL_TX_OFF; end