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In usual digital logic terminology, a latch is level triggered, in contrast to an edge triggered flip-flop.
The standard topology for edge triggered FF utilizes two latches in master-slave connection. You find it discussed in any useful digital logic text book. See below an implementation with double-throw transmission gates.
RN = active low reset. All blocks are basic CMOS circuits. The transmission gate designators are somehow confusing, in fact is CN the active high input and C active low, clarified by the C=0 marking.
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