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    Queries on JTAG interface for a CPLD based system

    Hi,

    I am trying to build a CPLD system which I plan to program using a JTAG parallel 3 cable. In the CPLD board design what should I connect for JTAG cable VCC supply? Since my board has 3.3v and 5.0v, I can use either. But the documentation here (page 4) says :

    “ The VCC supply level must match the I/O voltage level of the FPGA slave-serial configuration pins for best signal integrity.”

    Since my VCCIO of the CPLD is fixed to 3.3v for both banks, should I choose 3.3v. I am asking this because I have been using my JTAG parallel 3 cable with an FPGA system (Spartan 3 based) which provides 5 v supply to the cable.

    Also, should I connect the pins of male JTAG port of the CPLD board directly to the respective pins of CPLD IC or should I insert some resistance in-between the pins of the connector and IC? As per sheet 2 of link here, they have inserted 200 ohms in each signal line and have also given pull up resistors for TMS and TDI. Why so, and how are these resistances being calculated pls?

    Thanks and Regards,
    Arvind Gupta

    •   Alt10th March 2018, 18:31

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    Re: Queries on JTAG interface for a CPLD based system

    Hi,

    Vague informations.
    No PLD vendor and type name, no schematic.
    Informations like "The VCC supply level must.." ...we can not verify.
    We don't know if the 3.3V supplied signals are 5V tolerant.

    So what answer do you expect.
    I can only refer to the (to me unknown) darasheet.

    Klaus
    Please don´t contact me via PM, because there is no time to respond to them. Thank you.



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    Re: Queries on JTAG interface for a CPLD based system

    Thanks for the response.

    Quote Originally Posted by KlausST View Post
    No PLD vendor and type name, no schematic.
    PLD is Xilinx XC2C128 - VQ100 packaging

    Quote Originally Posted by KlausST View Post
    Informations like "The VCC supply level must.." ...we can not verify.
    We don't know if the 3.3V supplied signals are 5V tolerant.
    I had mentioned in my first post of the link to page 4 of Xilinx parallel port III programmer. Re inserting the link here for verifying the fact.

    Regarding the resistor values, I was referring to a Digilent schematic. I just wanted to know how the "JTAG/SPI Programming header" port series resistor values and pull up resistor values have been calculated (as in page 2 of the schematic; link re inserted here)

    Pls. let me know if you need any other inputs from my side.

    Thanks again,

    Arvind Gupta



    •   Alt11th March 2018, 07:42

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    Re: Queries on JTAG interface for a CPLD based system

    I have been using my JTAG parallel 3 cable with an FPGA system (Spartan 3 based) which provides 5 v supply to the cable.
    There's no Spartan 3 device with 5V compatibility at any pin. So even if the cable uses 5V supply, JTAG voltage is surely not exceeding 3.3V.

    200 ohm series resistors on JTAG lines is unusual. 20 to 50 ohms to absorb signal reflections would be normal. At the end of the day, the difference won't matter much if the JTAG speed is moderate.


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    Re: Queries on JTAG interface for a CPLD based system

    OK. Just one more thing. As per page 2 of the same schematic here, pin TMS of J8 has been pulled up to 3.3v with 10 K resistor. What could be the reason pls? I only require to program the CPLD.

    Thanks,
    Arvind Gupta.



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    Re: Queries on JTAG interface for a CPLD based system

    JTAG pins are often supplied with pull-up or pull-down resistors to avoid inadvertent JTAG commands issued by floating inputs. Also avoiding excessive current consumption of floating digital inputs can be a motivation. Many CPLD have however already built-in pull-up resistors on JTAG lines. Check the data sheet.


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    Re: Queries on JTAG interface for a CPLD based system

    Thanks. Yes, it is mentioned in the application notes (XAPP104 - page 1) that JTAG specifications require pull up resistors to be supplied internally for TDI and TMS pins but no particular value is required. Since I do not require to program multiple devices through JTAG in my case, I am avoiding the pull up resistors. Any comments are welcome.

    Regards,
    Arvind Gupta

    - - - Updated - - -

    Just one more question: Should I connect the cable header's TDI to CPLD's TDO and cable header's TDO to CPLD's TDI or is it a 1 :1 connection ie. cable header's TDI to CPLD's TDI and cable header's TDO to CPLD's TDO.

    Thanks again,
    Arvind Gupta.



    •   Alt29th March 2018, 11:01

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    Re: Queries on JTAG interface for a CPLD based system

    Xilinx says: (https://www.xilinx.com/support/answers/1408.html)
    CoolRunner-II devices have internal pull-ups on TDI, TMS, and TCK.
    Xilinx recommends using external pull-up resistors on the JTAG input pins, TDI, TMS, and TCK. The value of these resistors can be customized per your application and JTAG chain length; for a single device the value of 4.7k Ohm is suggested.
    Internal pull-up resistors are present on these JTAG input pins. However, external termination will allow for increased tolerance of noisy environments.
    As for the correct connection of your programming cable, refer to the user manual. Usually TDI refers to the cable line that has to be connected to the CPLD TDI input.


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