Continue to Site

Welcome to EDAboard.com

Welcome to our site! EDAboard.com is an international Electronics Discussion Forum focused on EDA software, circuits, schematics, books, theory, papers, asic, pld, 8051, DSP, Network, RF, Analog Design, PCB, Service Manuals... and a whole lot more! To participate you need to register. Registration is free. Click here to register now.

Register Log in

"Region_Fence_Violation" error in INNOVUS

Status
Not open for further replies.
A

Anklon

Member level 1
Joined
Dec 1, 2013
Messages
32
Helped
0
Reputation
0
Reaction score
0
Trophy points
6
Activity points
310
During PnR in INNOVUS, I am facing "Region_Fence_Violation" error.
I have checked my standard cell designs and could not find any particular problem. There is no information about this error in user guide. Can you explain me what this violation is and how could I solve this.
Thank for your time.
 

Not sure if you draw your fences wrong or if cells from one fence are landing on other fences.
 

Sorry for my ignorance , but I have no clear idea about fences. It will be helpful if you could provide me any link or resources to understand this properly.I may have made some mistakes in my layout. Thank you.
 

how and why did you put fences in your design if you don't know what they are? fences are hard constraint regions for placement. only cells for module A can be placed inside fence A.
 

Actually I did not put any fences (at least not knowingly). I just draw the layout according to our constrains, create netlist, export gds. It may be created during abstract generation automatically as a default option .

Sidenote: Is P&R boundary is the fence?
 

I have no clue what you are doing, I am incredibly lost. Fences are used in SoCs to constrain the placement solution. P&R boundary is a layer used in custom design to determine the cell width/height.

More details are needed. Are you doing a chip or a standard cell library? Are you certain you are using Innovus and not Virtuoso?
 

I am designing standard cell library in virtuoso . I'm just using Innovus to see that is it working right like following the grid , proper pin placement etc. Before the error message , I had no idea about fences. That's why I'm lost too.
 

Anklon said:
I am designing standard cell library in virtuoso . I'm just using Innovus to see that is it working right like following the grid , proper pin placement etc. Before the error message , I had no idea about fences. That's why I'm lost too.
Click to expand...

Sounds like your LEF generation has a problem then.
 
  • Like
Reactions: Anklon

    A

    Anklon

    Points: 2
    Helpful Answer Positive Rating
Status
Not open for further replies.

Similar threads

Part and Inventory Search

Welcome to EDABoard.com

Sponsor

Back
Top