Routing the ground on a 3 phase inverter

Hello,

i am working on a 4 layer pcb design on a circuit to drive a 3 phase bldc motor.

After some previous noise problems on my 2 layer design, i cam to the point where i want to go for a 4 layer.

So i have started working on the new pcb layout..

The goal is to minimize as much as possible the noise/ripple from the mosfet power stage, so it wont affect the control circuits

I started to follow this routing pattern

- top layer will provide +V for the power stage
- layer1 - will hold everything which is ground ( ground plane)
- layer2 - will hold some light power lines ( 5V, 3.3V and +12V for the FET drivers)
- bottom layer will hold the ouputs of the power stage


Right now i am focused on the ground layer, since i dont have galvanic isolation, everything is shared on the same ground net

Bellow is a proposal i am thinking of, i wonder if there are any disadvantages between the bellow picture, and a fully filled layer

Each case has its own limitations and constraints, so that you should have some reason to arrange ground planes this way but in general I would have preferred to put the power stage on one end of the board. These components deal with high energy levels that tend to radiate interference with more power to their vicinity.

The main reason why the power stage is not placed on the edge of the board, is because i use TO220 package and i need room for the radiator, plus on the edge of the board there is a screw type terminal connector



Keeping this "L" shape for the ground of the power stage transistors, i thought with this i can keep the high currents somehow away from the ground which references all the other small circuits.

Need to think about the nets that are crossing the ground split, power supply and control signals.

E.g. power supply is shorting the split through bypass capacitors. Control signals see the split voltage drop as common mode interference.

Hello FvM,

a good point which for the moment i missed out, i will reroute the ground layer, so the layer brakes just at the power transistors terminal, then the signals coming from the mosfet drivers, should be under the same "signal" ground.

What is very challenging is that i also try to avoid ground loops between ground layers

- - - Updated - - -

i am trying to keep away from the power vicinity every signal, and small power line

Regarding the ground split, i have attach a photo bellow

1 top layer ( not shown)
2 ground plane (purple)
3 intermediary layer ( green)
4 bottom layer (blue)

under the purple ground split, i placed another ground poor on the green layer which "hides" the split from the upper layer.

This way the bottom layer ( blue color) where i have my switching outputs will not interact with the ground split
Also this shields some current amplifier shunt which are located on the bottom side against the ground split

Is this a good practice?