Continue to Site

Welcome to EDAboard.com

Welcome to our site! EDAboard.com is an international Electronics Discussion Forum focused on EDA software, circuits, schematics, books, theory, papers, asic, pld, 8051, DSP, Network, RF, Analog Design, PCB, Service Manuals... and a whole lot more! To participate you need to register. Registration is free. Click here to register now.

Register Log in

Parameterized bitwidth

Status
Not open for further replies.
P

promach

Advanced Member level 4
Joined
Feb 22, 2016
Messages
1,199
Helped
2
Reputation
4
Reaction score
5
Trophy points
1,318
Activity points
11,636 
Code Verilog - [expand]
1
2
3

parameter C_PCI_DATA_WIDTH =128;  
 
rData <= #1 (rData << 4) - (C_PCI_DATA_WIDTH)'h0014001400140014;    // implements 16*x*x-20 for four different pieces of 32-bit data


How should we solve the syntax error around (C_PCI_DATA_WIDTH)'h0014001400140014 ??
 

First, this doesn't look to be parameterized.

Second, the comment is wrong unless there is a specific set of assumptions on the inputs.

Third, if such assumptions exist it is much better to write the code in a way the tools can use them.

for example, this is a 128 bit add (maybe, it looks like you are using 4 16 bit values which is 64b). It isn't clear that this never overflows/underflows into other 32b values.

I think you want to use for-generate with [32*myGenvar +: 32].
 

You didn't show the declaration of rData, but you may be able to just write:

rData <= #1 (rData << 4) - 'h0014001400140014;

Otherwise you can write
Code Verilog - [expand]
1
2
3

parameter C_PCI_DATA_WIDTH =128;  
typedef bit [C_PCI_DATA_WIDTH-1:0] PCI_DATA_t;
rData <= #1 (rData << 4) - PCI_DATA_t'('h0014001400140014);
 
Status
Not open for further replies.

Similar threads

Part and Inventory Search

Welcome to EDABoard.com

Sponsor

Back
Top