Welcome to our site! EDAboard.com is an international Electronics Discussion Forum focused on EDA software, circuits, schematics, books, theory, papers, asic, pld, 8051, DSP, Network, RF, Analog Design, PCB, Service Manuals... and a whole lot more! To participate you need to register. Registration is free. Click here to register now.
A real integrator can be respected to show finite DC gain, in other words a low frequency pole rather than a pole in the origin. It has probably also finite bandwidth, represented by one or more high frequency poles.
OK can the model be expressed for both the domains. If yes what will be their representation. As in previous post, please explain what value of a is to be considered for integrator
I think the question is pointless without referring to specific integrator implementations. Pole frequency can be µHz up to kHz, depending on the circuit and it's purpose. You can even have intentionally lossy integrators with pole frequency higher than kHz.
Let`s turn things clear; show us what is the circuit you are trying to simulate. In general simplifying assumptions are the best approach to take, as for example considering the integrator of the S/H as a constant flat value over the (short) time in which it operates, unless you are willing to check how your circuit would behave out of the range for which it was intended to be used.
Sorry there was a typo in #9. My question was general not specific to circuit design. I could understand from post #8, that integrator can be modeled as a miller type and can be approximated with TF = 1/r1c1 (s+1/r2c2). This is clear.
This site uses cookies to help personalise content, tailor your experience and to keep you logged in if you register.
By continuing to use this site, you are consenting to our use of cookies.
