Continue to Site

Welcome to EDAboard.com

Welcome to our site! EDAboard.com is an international Electronics Discussion Forum focused on EDA software, circuits, schematics, books, theory, papers, asic, pld, 8051, DSP, Network, RF, Analog Design, PCB, Service Manuals... and a whole lot more! To participate you need to register. Registration is free. Click here to register now.

System verilog - streaming-operator-multidimensional array to a stream of bits

Status
Not open for further replies.

albert1905

Newbie level 4
Joined
Mar 7, 2018
Messages
5
Helped
0
Reputation
0
Reaction score
0
Trophy points
1
Activity points
56
System verilog - streaming operator multidimensional array to stream of bits

Hi guys,
I cant figure out how to take multidimensional array such as:

bit unsigned [10:0] img [3:0][3:0];

And make this array as a stream of bits. Think of it as an 4X4 image that each pixel is 11 bits in my memory that I want to read, and I have 1 input pin that get my image as a stream of bits, I prefer if you have any idea how to do that, to get the data in streams of 11 bits (lets say I have a typedef). I want to declare an array like this in the testbench, and send this array as a stream of bits to my module that I want to test.
I'm working with quartus2 and with modelsim-sltera simulator.

I tried to do any variation i saw online, but nothing useful:

stream = { >> {img}};
or

stream = { << {img}};

defined stream as bits or int , exc.

edit: the errors I got from the above attempts were identical:

"near text ">>"; expecting an operand"

Thanks a lot for any help.

- - - Updated - - -

sorry, I missed the fact that it is analog forum Ill be happy if this post will pass to the right forum.
 

Re: System verilog - streaming operator multidimensional array to stream of bits

Since this is for a testbench why not use a nested for loop with a time control statement in the inner loop to serially output the bits.

Just checked and the streaming operator is not used like you are showing it's on the wrong side of the assignment to begin with and it's not for generating a stream of bits.
see this
 
Status
Not open for further replies.

Part and Inventory Search

Welcome to EDABoard.com

Sponsor

Back
Top