promach
Advanced Member level 4
I am facing this error "Error: Error: Can't perform simulation of IP file /home/phung/Documents/riffa/fpga/altera/de4/DE4Gen2x8If128/ip/PCIeGen2x8If128_core.v because no simulation model files were detected". However, from the screenshot below, I have included PCIeGen2x8If128_core.vo IP functional simulation model file as described in https://www.altera.com/en_US/pdfs/literature/hb/qts/qts-qps-5v3.pdf#page=16
What else had I missed ?
What else had I missed ?
Error: Error: Can't perform simulation of IP file /home/phung/Documents/fpga_overlay/riffa/fpga/altera/de4/DE4Gen2x8If128/ip/PCIeGen2x8If128_core.v because no simulation model files were detected
Error: Error: You did not generate the simulation model files or you generated the IP file using an older version of Intel FPGA IP which is not supported by RTL NativeLink Simulation
Error: Error: Regenerate the IP and simulation model files using the latest version of Intel FPGA IP for RTL NativeLink Simulation flow to function correctly
Error: Error: NativeLink simulation flow was NOT successful