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[Verilog] Task inputs assigned right before task call - Race condition

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pigtwo

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Hello all,

I have a fairly simple question about tasks with inputs. I've been working on this problem where I assign some values to a register then use those values as the input to a task. I've found that when I call the task the values it takes is the previous value of the input. I created an example to quickly show what I'm saying. In the below module I assign 'a' a value then give 'a' to a task which gives it to 'b'.
Code Verilog - [expand]
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module task_test( );
 
    reg clk;
    reg[7:0] a, b;
 
    initial begin
        forever #5 clk = ~clk;  
    end
 
    initial begin
        clk = 0;
        a = 0;
        b = 0;
        
        #10
        while(1) begin
            a = a + 1;
            give(a,b);
        end
    end
 
    task give;
    input[7:0] x;
    output[7:0] y;
        begin
        y = x;  
        @(posedge clk);
        end 
    endtask
 
endmodule


Below is the simulation output:
sim.PNG

As you can see the task seems to get the previous value of 'a'. I've found the solution to this by adding a delay before I call the task but I'm curious about why this happens. Is it the simulator reording which statements are called first or is there something I don't understand about calling tasks? This seems strange to me because I'm using blocking assignments so the 'a = a + 1;' should have to finish before going to the task so I'm not sure why the task is getting the previous value. I must be missing something here.

Thank you!
 
Last edited:

You are missing the fact that the value of y does not get copied to auntil the task exits, which is one clock cycle later.
 
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    pigtwo

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