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What is low background Iddq in device?

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It's explained in the top paragraph of the same page:

Sub-threshold (IOFF) transistor leakage is the primary contributor to the background
leakage current. Outside of the very deep submicron regime, this leakage is
extremely low compared the leakage level required to cause a circuit failure. As sub-
threshold leakage increases in the deep submicron regime. lDDQ testability will
become limited due to the high level of background current.
Click to expand...

"For devices,which do not exhibit low background Iddq..." means "devices not belonging to the very deep submicron regime", i.e. devices generated by process sizes >≈ 100nm .
 

IDDQ refers to a "quality" test method for digital parts
where supply current is monitored per functional vector
looking for state dependent out-of-family current. It is
a way to cull "functional, but a certain class of not-right"
from the population - say, a gate with a gate ox defect
that "works" but might drift worse (and you have no way
of knowing - only knowing something is not right, so kill
it.

Obviously this works best when nobody leaks or they
all leak the same.
 

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