[SOLVED] Determining the frequency of nco implemented in FPGA

dipin · Feb 28, 2018

hi,

i implemented a NCO(numerically controlled oscillator) in fpga.

according to the equation , its frequency f = (controllword x f clock)/ 2^N;

here i am using control word =50 (step size);f clock= 65Mhz; N=12 bits.. so frequency must be around 793khz.

but i am getting frequency around 990 khz, when i use a oscilloscope to measure it ...

can anybody give any suggestions on this ??

any help is really appreciated

Thanks and Regards

FvM · Feb 28, 2018

Re: determining the frequency of nco implemented in fpga

793 kHz is correct. Possible explanations
- wrong nco code
- wrong clock frequency
- wrong frequency measurement

KlausST · Feb 28, 2018

Re: determining the frequency of nco implemented in fpga

Hi,

It may be 81.1MHz input frequency...maybe there is a PLL involved?
Control word = 62?

A simulation will help you to find the error.

Measurement problem: How did you measure it? Did you cross check the input frequency with your scope?
You know that the output frequency contains some jitter...but usually not in that error range.

Klaus

dipin · Mar 1, 2018

Re: determining the frequency of nco implemented in fpga

hi ,
i am using a pll to generate 65 Mhz clock. my board clock is 50 Mhz .i am giving it to the pll to generate 65 mhz and then this 65 Mhz running the design.
control word is 50 only and i dont know what is exactly the output of the pll. i am using it for 65 mhz.. but i will check it somehow.

i cross checked the oscilloscope and its measurements are fine..it contains some jitter bit still ok ...

thanks much for the suggestions fvm and klausst..

if there is a pll then is it going to be problem??

maybe there is a PLL involved?

actually i am using one like i explained above...
can you please tell me why so..

thanks

KlausST · Mar 1, 2018

Re: determining the frequency of nco implemented in fpga

Hi,

No, my idea was that there is 65MHz input to your FPGA ...
And some kind of hidden PLL generates 81.1MHz

But this seems not to be the case.

But you didn't answer how you measured the 990kHz. There are several ways to do this with a scope...some are more precise than the others.

A scope picture could help.

Klaus

dipin · Mar 1, 2018

Re: determining the frequency of nco implemented in fpga

hi,

above i am connecting a probe to ada card and connected to oscilloscope

i think pll is the problem. anybody had any idea how to fix it

thanks and regards

KlausST · Mar 1, 2018

Re: determining the frequency of nco implemented in fpga

Hi,

I´m surprised. The scope picture shows a sinewave, but I expected a square wave as NCO output.

Klaus

dipin · Mar 1, 2018

Re: determining the frequency of nco implemented in fpga

hi,
really sorry,,

i am generating a sine wave using CORDIC algorithm...

so above equation is applicable to it or not ?

thanks and regards

Doka · Mar 1, 2018

Re: determining the frequency of nco implemented in fpga

1. could you for debug purposes output to oscilloscope signal Fclk/64 ?

2. N=12bit - not enough resolution for precise F setup, please use 32bit acc (and 12 bit MSB from this ACC) for fine set desired F

- - - Updated - - -

KlausST said:
Hi,
I´m surprised. The scope picture shows a sinewave, but I expected a square wave as NCO output.

That's regular waveform from DDS kind of NCO.
Nothing suspicious

KlausST · Mar 1, 2018

Re: determining the frequency of nco implemented in fpga

Hi,

i think pll is the problem. anybody had any idea how to fix it

"I think" ... why don´t you verify it by simply connectig the cope to the PLL output?
And if you don´t have the signal at an FPGA pin, this shouldn´t be a big deal.

Klaus

dipin · Mar 1, 2018

Re: determining the frequency of nco implemented in fpga

HI
i tried to give the output to dac but not working....
so i tried using siganltap but i am getting a strange signals which duty cycle is varying....please see the screenshot

is it like a bug in signal tap ??
i added the signals from pre synthesis list. you can see the clock going to the pll are low and it will never became , but pll is giving output..
refclock is 50 mhz and outclock is 65 mhz

there are my clock from fpga,, basically thaat also not visible in signal tap and its there because design is working...

please give your suggestions

thanks and regards

KlausST · Mar 1, 2018

Re: determining the frequency of nco implemented in fpga

Hi,

with no input signal the PLL may output any frequency....It simply is not locked and the VCO frequency seems to saturate at the upper end.
--> solve the missing 50MHz (mind the big difference to 50mHz) at the PLL input problem.

Please verify your signals step by step:
* 50MHz input
* 65MHz PLL output (you may get a PLL_status signals like "locked". Do you check them in your application? What do they say?)
* NCO output

* ... CORDIC and DAC only if the above is working well, otherwise it´s just confusing.

Klaus

FvM · Mar 1, 2018

Re: determining the frequency of nco implemented in fpga

Without telling the signaltap acquisition clock frequency, the screenshots in post #11 are just useless. Why don't you show a bigger picture of the design?

strange signals which duty cycle is varying

Expectable if the acquisition clock isn't an even multiply of the output frequency.

dipin · Mar 1, 2018

Re: determining the frequency of nco implemented in fpga

hi,
before i was using acquisition clock as 50 mhz and all those clock to pll are also 50 MHz. but now i changed to MHz which is the output of pll. now i am able to see the system clock. but they are not in 50% duty cycle. why it is like that ???
they are just clock from fpga ...i didn't done anything its generated from fpga and why its duty cycle is not 50%..
that's why i asked that is it because signal tap not able to catch it or not ?

input OSC_50_B3B;
input OSC_50_B4A;
input OSC_50_B5B;
input OSC_50_B8A;

are the system clocks.

from manual

thanks and regards

FvM · Mar 1, 2018

Re: determining the frequency of nco implemented in fpga

i was using acquisition clock as 50 mhz and all those clock to pll are also 50 MHz. but now i changed to MHz which is the output of pll.

??? What is the acquisition frequency, actually?

dipin · Mar 1, 2018

Re: determining the frequency of nco implemented in fpga

hi
really sorry fvm. now its 65 mhz.
but why system clock dont have 50 % duty cycle

thanks

KlausST · Mar 1, 2018

Re: determining the frequency of nco implemented in fpga

Hi,

but why system clock dont have 50 % duty cycle

I don´t know.
If I wanted to know this I´d read the clock generator (PLL) documentation.
Usually there is
* an input clock divider
* a VCO
* a VCO ouput clock divider for the phase comparator
* a phase comparator with filter to control the VCO
* a VCO output clock divider for the user output <-- this may be the cause of jitter (my assumption)

Klaus

ads-ee · Mar 1, 2018

Re: determining the frequency of nco implemented in fpga

dipin said:
hi
really sorry fvm. now its 65 mhz.
but why system clock dont have 50 % duty cycle

thanks

Your previous descriptions seem to imply you are sampling 50 MHz signals using the 65 MHz PLL output, that is not going to work and will result in the non-50% duty cycle captures of the 50 MHz clock.

Also your description of using the input 50MHz clock to sample itself is also not going to work. I think you need to learn more about digital design and working with asynchronous clock domains, as I think this is the fundamental problem you are having.

dipin · Mar 2, 2018

Re: determining the frequency of nco implemented in fpga

thanks ads-ee..
right on target!!!!
i didnt thought about it,,, may be because iam a newbee..

now i am verifying that all the clocks are good,.. but no way to check weather the output of pll is 65mhz (the one which runs the design)or not. because may be my oscilloscope is wont be able to pick such high frq signals,,, it was picking it when i changed the frequency to 10 mhz...
but i dont think so it must be checked because it is an pll ip from quartus. so no need to check right, if it works fine at 20mhz then it should work at 65 mhz ...
can you share your opinion about this

thanks and regards

KlausST · Mar 2, 2018

Re: determining the frequency of nco implemented in fpga

Hi,

your scope is a 100MHz type. So it should be able to show 65MHz.

Adjust the trigger level.
Check input setup. Don`t use "noise suppression" or"bandwidth limited" or similar setup.

Klaus

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[SOLVED] Determining the frequency of nco implemented in FPGA

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