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VHDL generate multi-instances with differet generic values

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sarang5s5

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In VHDL, is it possible to generate multiple instances of a generic instance with different generic values ?
for example, a simple generic counter (say generic WIDTH = 2) instantiated multiple times (in loop or conditionally) in a top level entity, with its different generic values.
Is it possible ? If yes, please help on the same.
 

yes it's possible. For example in a generate loop:

Code VHDL - [expand]
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inst_gen : for i in 1 to 10 generate
  counter_inst : entity work.generic_counter
  generic map ( DWIDTH => i );
end generate inst_gen;
 

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