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DDR2 memory controller in FPGA

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fpga93

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Hi all,

I am to design a DDR2 memory controller on Altera FPGA, but the ip core seems too complex with an extra PHY layer helping to interface with external memory device.I want to design a simple controller core based on an FSM. I want to know if thats possible without a PHY layer as Altera documentation states.If anyone has a previous experience in designing their own DDR2 mmwory controller ip core. Please do help.

Thanks,
fpga93
 

Re: Ddr2 memory controller in fpga

What is your purpose? Do you need a very specific memory controller benefit that you can't get from the stock IP? Are you only concerned with lower performance from the DDR2?

You can make a custom IP DDR2 controller, but you'll likely be bringing more of the practical issues from the stock iP. If you don't need a custom IP, this becomes harder to justify.
 

Re: Ddr2 memory controller in fpga

Hi,

but the ip core seems too complex with an extra PHY layer helping to interface with external memory device
It seems you want a similar interace like a "parallel SRAM" interface. But DRAM isn´t that simple.

I´m not really up to date what different DRAMS there are.

My recommendation:
* use the existing IP
* or read through your DDR RAM datasheet to find out that it is somehow complex. Because there may be times when you can´t access the RAM because it is busy with a refresh cycle...and how to handle tihs. Maybe delayed (waiting) processor or installing RAM buffers.

Klaus
 

Re: Ddr2 memory controller in fpga

I am to design a DDR2 memory controller on Altera FPGA, but the ip core seems too complex with an extra PHY layer helping to interface with external memory device.I want to design a simple controller core based on an FSM. I want to know if thats possible without a PHY layer as Altera documentation states.

I think you understand that most of the timing or scheduling of control signals is taken care by the PHY of the memory controller.
In order to achieve the proper/higher speeds the design timing involved gets more complex. The memory controller IP cores which are available tend to hide these complexities from the user and this means means faster time to market for the end product.
It would be possible to make your own controller from scratch but you would be limited in the fmax you could achieve as you would have to use the standard FPGA IO logic blocks (no PHY).
 

Re: Ddr2 memory controller in fpga

Thanks for all your replies,

I know the IP Core is apt for controlling the memory device, but it is too complex and hard to understand. I will be using the same for real world application but as far as my course project goes, I would just be required to build the controller with essential understanding of the translation of the client requests at one end to corresponding command sequences at the DDR end and effective testbench to prove its working. I wanted to know whether even if i am not able to achieve the maximum operational frequency, whether such an implementation of a DDR memory controller would make sense?
 

Re: Ddr2 memory controller in fpga

I would just be required to build the controller with essential understanding of the translation of the client requests at one end to corresponding command sequences at the DDR end and effective testbench to prove its working.
...well then go ahead!

There are some examples at https://opencores.org/projects under "Memory core".
There are also some under GitHub.
 

Re: Ddr2 memory controller in fpga

If you want to use this as a learning experience to understand how DRAM works and how to interface with it then I would say go for it. Otherwise, if you're looking for performance I think you should use the vendor IP.
 

Re: Ddr2 memory controller in fpga

Thanks for all your replies,

I know the IP Core is apt for controlling the memory device, but it is too complex and hard to understand. I will be using the same for real world application but as far as my course project goes, I would just be required to build the controller with essential understanding of the translation of the client requests at one end to corresponding command sequences at the DDR end and effective testbench to prove its working. I wanted to know whether even if i am not able to achieve the maximum operational frequency, whether such an implementation of a DDR memory controller would make sense?

do you mean that you just need command sequences and don't care about the actual physical IO concerns? One part of the controller is the initial and continuous calibration of the interface.
 

Re: Ddr2 memory controller in fpga

FPGA have dedicated hardware functions for DDR2 RAM DQ and DQS signals and respective timing calibration. Controlling this functions involves much of the DDR2 IP complexity. A possible solution for a principal demonstration interface could be to run the DDR2 RAM at it's minimal clock frequency (e.g. 125 MHz, review your datasheets) and try without dedicated DQ/DQS hardware.
 

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