How does DQS make it possible to reach higher data rates in DDR DRAMs?

SDR DRAM does not have DQS signal, this is called data strobe and data is called DQ. On the other hand, DDR RAMs have DQS signal which makes them somehow achieve higher data rates.

A single DQS may exist for 4, 8, 16 or even 32 DQ signals. Why do we need a DQS? It seems to behave similar to clock. Also, why don't we always have a single DQS for all DQ always, regardless of how many DQ lines exist?

DQS is a strobe for reading back data, it improves performance as it is delay matched with the DQ lines producing a source synchronous interface.

The number of DQS is because if you try and delay match a very large bus it is much harder to match all lines closely whereas only having to delay match 8 DQ lines, 1 DM and the DQS means you are only having to delay match 11 signals instead of something like 80 signals for a 64-bit wide DDR DRAM interface.

But the data must reach the other end before the next clock edge, isn't it? Why can't we just use clk?

The point is with the fastest DDR speeds the clock period is ~500 ps (2133 MHz for DDR4). So if we assume 180 ps/in propagation delay and traces on the order of 3 inch (after delay matched for a byte lane) we end up with 540 ps of delay from the DDR4 chip to the reading device. Basically you just lost any chance to use the same clock that is used as the input DDR clock and the device that is receiving the data.

On DIMMs the routing is usually done fly-by and the routes may end up being much longer then 3 in after including the DIMM routing the connector and the PCB routing from the connector to the memory controller. This would result in the data being read showing up at the controller in the following clock cycle.

This is the reason that high speed interfaces use source synchronous interfaces or some sort of clock recovery method (clock embedded in the serial data). Using clock recovery you can run the frequency of the signals way past the "bus" frequencies for source synchronous interfaces as there is no issue with skew between clock and data signals.