Continue to Site

Welcome to EDAboard.com

Welcome to our site! EDAboard.com is an international Electronics Discussion Forum focused on EDA software, circuits, schematics, books, theory, papers, asic, pld, 8051, DSP, Network, RF, Analog Design, PCB, Service Manuals... and a whole lot more! To participate you need to register. Registration is free. Click here to register now.

Register Log in

Fixing LVS Errors in Synopsys IC Compiler

Status
Not open for further replies.
D

dayana42200

Junior Member level 3
Joined
Feb 9, 2018
Messages
31
Helped
0
Reputation
0
Reaction score
1
Trophy points
6
Activity points
315
Hi everyone.

How can I fix these LVS errors?
Code: 
-- LVS START : --
Total area error in layer 0 is 0.  Elapsed =    0:00:00, CPU =    0:00:00
Total area error in layer 1 is 0.  Elapsed =    0:00:00, CPU =    0:00:00
Total area error in layer 2 is 0.  Elapsed =    0:00:00, CPU =    0:00:00
Total area error in layer 3 is 0.  Elapsed =    0:00:00, CPU =    0:00:00
Total area error in layer 4 is 0.  Elapsed =    0:00:00, CPU =    0:00:00
Total area error in layer 5 is 0.  Elapsed =    0:00:00, CPU =    0:00:00
Total area error in layer 6 is 0.  Elapsed =    0:00:00, CPU =    0:00:00
Total area error in layer 7 is 0.  Elapsed =    0:00:00, CPU =    0:00:00
Total area error in layer 8 is 0.  Elapsed =    0:00:00, CPU =    0:00:00
Total area error in layer 9 is 0.  Elapsed =    0:00:00, CPU =    0:00:00
Total area error in layer 10 is 0.  Elapsed =    0:00:00, CPU =    0:00:00
Total area error in layer 11 is 0.  Elapsed =    0:00:00, CPU =    0:00:00
Total area error in layer 12 is 0.  Elapsed =    0:00:00, CPU =    0:00:00
Total area error in layer 13 is 0.  Elapsed =    0:00:00, CPU =    0:00:00
Total area error in layer 14 is 0.  Elapsed =    0:00:00, CPU =    0:00:00
Total area error in layer 15 is 0.  Elapsed =    0:00:00, CPU =    0:00:00
ERROR : PortInst U27 VSS doesn't connect to any net.

ERROR : PortInst U25 VSS doesn't connect to any net.

ERROR : PortInst Algorithm/Ixij/Mi1j/U20 VSS(9381) in net VSS(26660) is floating.

ERROR : PortInst Algorithm/Ixij/Mi1j/U16 VSS(9999) in net VSS(26660) is floating.

ERROR : OUTPUT PortInst Algorithm/Ixij/Mi1j/add_0_root_add_0_root_add_20_2/U1_7 CO doesn't connect to any net.

ERROR : OUTPUT PortInst Algorithm/Mij/Iyi1j1/add_16/U1_7 CO doesn't connect to any net.

ERROR : PortInst U25 VDD doesn't connect to any net.

ERROR : OUTPUT PortInst Algorithm/Ixij/Ixi1j/add_16/U1_7 CO doesn't connect to any net.

ERROR : OUTPUT PortInst Algorithm/Iyij/Mij1/add_0_root_add_0_root_add_17_2/U1_7 CO doesn't connect to any net.

ERROR : PortInst Algorithm/Ixij/Ixi1j/U9 VSS(10306) in net VSS(26660) is floating.

ERROR : OUTPUT PortInst Algorithm/Iyij/Iyij1/add_19/U1_7 CO doesn't connect to any net.

ERROR : OUTPUT PortInst Algorithm/Mij/Ixi1j1/add_16/U1_7 CO doesn't connect to any net.

ERROR : OUTPUT PortInst Algorithm/Mij/Mi1j1/add_16/U1_7 CO doesn't connect to any net.

ERROR : PortInst U30 VDD doesn't connect to any net.

ERROR : PortInst U42 VDD doesn't connect to any net.

ERROR : PortInst U36 VDD doesn't connect to any net.

ERROR : PortInst U34 VDD doesn't connect to any net.

ERROR : PortInst U16 VDD doesn't connect to any net.

ERROR : PortInst LUT/U9 VDD(4767) in net VDD(26659) is floating.

ERROR : PortInst U32 VDD doesn't connect to any net.

ERROR : There are more errors than default Max Error Number 20.
** Total Floating ports are 20.
** Total Floating Nets are 0.
ERROR : Logical Net VSS is open.
        Node 661 is in the region ((2,2),(117,114)).
        Node 715 is in the region ((58,5),(91,5)).
        Node 720 is in the region ((42,5),(57,5)).
        Node 733 is in the region ((17,5),(35,5)).
        Node 726 is in the region ((36,5),(38,5)).
        Node 724 is in the region ((39,5),(41,5)).
        Node 699 is in the region ((93,5),(114,5)).
        Node 174 is in the region ((17,78),(19,79)).
        Total seperated nodes are 8.
        Potential connection region ((18, 4), (94, 79)).
** This OPEN is caused by PIN. Please check with FLOATING PIN option.
ERROR : Logical Net VDD is open.
        Node 693 is in the region ((3,3),(116,113)).
        Node 18 is in the region ((56,111),(107,112)).
        Node 26 is in the region ((35,110),(43,112)).
        Node 28 is in the region ((30,110),(34,112)).
        Node 21 is in the region ((49,111),(54,112)).
        Total seperated nodes are 5.
        Potential connection region ((33, 110), (57, 113)).
** This OPEN is caused by PIN. Please check with FLOATING PIN option.
** Total OPEN Nets are 2.
** Total Electrical Equivalent Error are 0.
** Total Must Joint Error are 0.

-- LVS END : --
Elapsed =    0:00:00, CPU =    0:00:00
 
Last edited by a moderator:

dayana42200 said:
Hi everyone.

How can I fix these LVS errors?
Code: 
-- LVS START : --
Total area error in layer 0 is 0.  Elapsed =    0:00:00, CPU =    0:00:00
Total area error in layer 1 is 0.  Elapsed =    0:00:00, CPU =    0:00:00
Total area error in layer 2 is 0.  Elapsed =    0:00:00, CPU =    0:00:00
Total area error in layer 3 is 0.  Elapsed =    0:00:00, CPU =    0:00:00
Total area error in layer 4 is 0.  Elapsed =    0:00:00, CPU =    0:00:00
Total area error in layer 5 is 0.  Elapsed =    0:00:00, CPU =    0:00:00
Total area error in layer 6 is 0.  Elapsed =    0:00:00, CPU =    0:00:00
Total area error in layer 7 is 0.  Elapsed =    0:00:00, CPU =    0:00:00
Total area error in layer 8 is 0.  Elapsed =    0:00:00, CPU =    0:00:00
Total area error in layer 9 is 0.  Elapsed =    0:00:00, CPU =    0:00:00
Total area error in layer 10 is 0.  Elapsed =    0:00:00, CPU =    0:00:00
Total area error in layer 11 is 0.  Elapsed =    0:00:00, CPU =    0:00:00
Total area error in layer 12 is 0.  Elapsed =    0:00:00, CPU =    0:00:00
Total area error in layer 13 is 0.  Elapsed =    0:00:00, CPU =    0:00:00
Total area error in layer 14 is 0.  Elapsed =    0:00:00, CPU =    0:00:00
Total area error in layer 15 is 0.  Elapsed =    0:00:00, CPU =    0:00:00
ERROR : PortInst U27 VSS doesn't connect to any net.

ERROR : PortInst U25 VSS doesn't connect to any net.

ERROR : PortInst Algorithm/Ixij/Mi1j/U20 VSS(9381) in net VSS(26660) is floating.

ERROR : PortInst Algorithm/Ixij/Mi1j/U16 VSS(9999) in net VSS(26660) is floating.

ERROR : OUTPUT PortInst Algorithm/Ixij/Mi1j/add_0_root_add_0_root_add_20_2/U1_7 CO doesn't connect to any net.

ERROR : OUTPUT PortInst Algorithm/Mij/Iyi1j1/add_16/U1_7 CO doesn't connect to any net.

ERROR : PortInst U25 VDD doesn't connect to any net.

ERROR : OUTPUT PortInst Algorithm/Ixij/Ixi1j/add_16/U1_7 CO doesn't connect to any net.

ERROR : OUTPUT PortInst Algorithm/Iyij/Mij1/add_0_root_add_0_root_add_17_2/U1_7 CO doesn't connect to any net.

ERROR : PortInst Algorithm/Ixij/Ixi1j/U9 VSS(10306) in net VSS(26660) is floating.

ERROR : OUTPUT PortInst Algorithm/Iyij/Iyij1/add_19/U1_7 CO doesn't connect to any net.

ERROR : OUTPUT PortInst Algorithm/Mij/Ixi1j1/add_16/U1_7 CO doesn't connect to any net.

ERROR : OUTPUT PortInst Algorithm/Mij/Mi1j1/add_16/U1_7 CO doesn't connect to any net.

ERROR : PortInst U30 VDD doesn't connect to any net.

ERROR : PortInst U42 VDD doesn't connect to any net.

ERROR : PortInst U36 VDD doesn't connect to any net.

ERROR : PortInst U34 VDD doesn't connect to any net.

ERROR : PortInst U16 VDD doesn't connect to any net.

ERROR : PortInst LUT/U9 VDD(4767) in net VDD(26659) is floating.

ERROR : PortInst U32 VDD doesn't connect to any net.

ERROR : There are more errors than default Max Error Number 20.
** Total Floating ports are 20.
** Total Floating Nets are 0.
ERROR : Logical Net VSS is open.
        Node 661 is in the region ((2,2),(117,114)).
        Node 715 is in the region ((58,5),(91,5)).
        Node 720 is in the region ((42,5),(57,5)).
        Node 733 is in the region ((17,5),(35,5)).
        Node 726 is in the region ((36,5),(38,5)).
        Node 724 is in the region ((39,5),(41,5)).
        Node 699 is in the region ((93,5),(114,5)).
        Node 174 is in the region ((17,78),(19,79)).
        Total seperated nodes are 8.
        Potential connection region ((18, 4), (94, 79)).
** This OPEN is caused by PIN. Please check with FLOATING PIN option.
ERROR : Logical Net VDD is open.
        Node 693 is in the region ((3,3),(116,113)).
        Node 18 is in the region ((56,111),(107,112)).
        Node 26 is in the region ((35,110),(43,112)).
        Node 28 is in the region ((30,110),(34,112)).
        Node 21 is in the region ((49,111),(54,112)).
        Total seperated nodes are 5.
        Potential connection region ((33, 110), (57, 113)).
** This OPEN is caused by PIN. Please check with FLOATING PIN option.
** Total OPEN Nets are 2.
** Total Electrical Equivalent Error are 0.
** Total Must Joint Error are 0.

-- LVS END : --
Elapsed =    0:00:00, CPU =    0:00:00
Click to expand...

Without seeing your layout and schematic it's tough to say. Some CO opens miggh be fine if they are not used, but VDD/VSS points out to a missing power connection.
 

How can I fix the power connection? The layout is generated based on Verilog HDL design based on Design Vision ddc file. Can I draw manually?
 

You should use derive_pg_connection command to make logical connection of VDD/VSS pins to power/ground nets.
And use preroute_standard_cells to make physical connection of standard cells.
And command create_power_straps for building power/ground mesh in your design.
 
dayana42200 said:
How can I fix the power connection? The layout is generated based on Verilog HDL design based on Design Vision ddc file. Can I draw manually?
Click to expand...

I don't even know how to reply to this. Are you saying you don't have power rings/stripes/rails?
 

Status
Not open for further replies.

Similar threads

Part and Inventory Search

Welcome to EDABoard.com

Sponsor

Back
Top