Continue to Site

Welcome to EDAboard.com

Welcome to our site! EDAboard.com is an international Electronics Discussion Forum focused on EDA software, circuits, schematics, books, theory, papers, asic, pld, 8051, DSP, Network, RF, Analog Design, PCB, Service Manuals... and a whole lot more! To participate you need to register. Registration is free. Click here to register now.

instruction memory module control signals

Status
Not open for further replies.

promach

Advanced Member level 4
Joined
Feb 22, 2016
Messages
1,199
Helped
2
Reputation
4
Reaction score
5
Trophy points
1,318
Activity points
11,636
For https://gist.github.com/promach/c8d9e576971e327495b13380cc235bff#file-inst_mem-v-L36 and https://i.imgur.com/wal9hRP.png , do you guys have any comment on why 'ctrl' use 'logical OR' ?

Screenshot_wal9hRP.png

Code:
module inst_mem(clk, rst, valid, tag, ins, inst, valid_out);

	parameter DATA_WIDTH = 32;
	parameter INS_WIDTH	= 40;
	parameter INST_WIDTH	= 32;
	parameter TAG_WIDTH	= 8;
	
	parameter RAM_WIDTH = 32;
  	parameter RAM_ADDR_BITS = 5;

	input clk;
	input rst;
	input valid;
	input [TAG_WIDTH-1:0] tag;
	input [INS_WIDTH-1:0] ins;
	output[RAM_WIDTH-1:0] inst;
	output valid_out; //control_d7

	reg control = 0;
	reg control_d1, control_d2, control_d3, control_d4, control_d5, control_d6, control_d7, control_d8, control_d9;
	
	assign valid_out = control_d7; //Determine II, latency (control_d6)

/******************** IMEM *************************/	 
	wire wea, ctrl;
	reg wea_r=0;
	reg [RAM_WIDTH-1:0] din=0;
	reg [RAM_ADDR_BITS-1:0] inst_addr = 0;
	reg [RAM_ADDR_BITS-1:0] pc = 0;
	reg [RAM_ADDR_BITS-1:0] addr = 0;
//	wire [RAM_ADDR_BITS-1:0] addr = 0;
	
	//assign ena  = (ins!=0);
	assign wea  = (tag == ins[39:32]) & (ins!=0) & (~ctrl);

	assign ctrl = control | control_d1;	//Keep the register after LUTRAM based IM
//	assign ctrl = control_d1 | control_d2;	//Delete the register after LUTRAM based IM
	
	memtest IMEM (clk, wea_r, din, addr, inst);
	
	always @(posedge clk)
	begin
		wea_r <= wea;
		din <= ins[RAM_WIDTH-1:0];
		addr <= (ctrl) ? pc : inst_addr;
	end
	
//	assign addr = (ctrl) ? pc : inst_addr;
	
	always @(posedge clk) 
	begin
		if (wea) begin
		 	inst_addr <= inst_addr + 1;
			//imem[inst_addr] <= ins[RAM_WIDTH-1:0];
	      	end
		
		if (ctrl) begin	//control
			//inst_r1 <= imem[pc];
			//inst 	  <= inst_r1;
			pc <= pc + 1;
		end
		
		else
			pc <= 0;
   	end	

/******************** IMEM *************************/	


reg valid_d1;
reg valid_d2;
reg valid_d3;
reg valid_d4;
reg valid_d5;
reg valid_d6;
reg valid_d7;
reg valid_d8;
reg valid_d9;
reg valid_d10;
reg valid_d11;
reg valid_d12;
reg valid_d13;
reg valid_d14;
reg valid_d15;
reg valid_d16;

assign valid_p = ~valid_d1 & valid; //generate a pulse when posedge valid

always @(*)
case (inst_addr)
	4'b0000: control <= 0;
	4'b0001: control <= (valid) & (~valid_d1);
	4'b0010: control <= ((valid) & (~valid_d1)) | ((valid_d1) & (~valid_d2));
	4'b0011: control <= ((valid) & (~valid_d1)) | ((valid_d1) & (~valid_d2)) | ((valid_d2) & (~valid_d3));
	4'b0100: control <= ((valid) & (~valid_d1)) | ((valid_d1) & (~valid_d2)) | ((valid_d2) & (~valid_d3)) | ((valid_d3) & (~valid_d4));
	4'b0101: control <= ((valid) & (~valid_d1)) | ((valid_d1) & (~valid_d2)) | ((valid_d2) & (~valid_d3)) | ((valid_d3) & (~valid_d4)) | ((valid_d4) & (~valid_d5));
	4'b0110: control <= ((valid) & (~valid_d1)) | ((valid_d1) & (~valid_d2)) | ((valid_d2) & (~valid_d3)) | ((valid_d3) & (~valid_d4)) | ((valid_d4) & (~valid_d5)) | ((valid_d5) & (~valid_d6));
	4'b0111: control <= ((valid) & (~valid_d1)) | ((valid_d1) & (~valid_d2)) | ((valid_d2) & (~valid_d3)) | ((valid_d3) & (~valid_d4)) | ((valid_d4) & (~valid_d5)) | ((valid_d5) & (~valid_d6)) | ((valid_d6) & (~valid_d7));
	4'b1000: control <= ((valid) & (~valid_d1)) | ((valid_d1) & (~valid_d2)) | ((valid_d2) & (~valid_d3)) | ((valid_d3) & (~valid_d4)) | ((valid_d4) & (~valid_d5)) | ((valid_d5) & (~valid_d6)) | ((valid_d6) & (~valid_d7)) | ((valid_d7) & (~valid_d8));
	4'b1001: control <= ((valid) & (~valid_d1)) | ((valid_d1) & (~valid_d2)) | ((valid_d2) & (~valid_d3)) | ((valid_d3) & (~valid_d4)) | ((valid_d4) & (~valid_d5)) | ((valid_d5) & (~valid_d6)) | ((valid_d6) & (~valid_d7)) | ((valid_d7) & (~valid_d8)) | ((valid_d8) & (~valid_d9));
	4'b1010: control <= ((valid) & (~valid_d1)) | ((valid_d1) & (~valid_d2)) | ((valid_d2) & (~valid_d3)) | ((valid_d3) & (~valid_d4)) | ((valid_d4) & (~valid_d5)) | ((valid_d5) & (~valid_d6)) | ((valid_d6) & (~valid_d7)) | ((valid_d7) & (~valid_d8)) | ((valid_d8) & (~valid_d9)) | ((valid_d9) & (~valid_d10));
	4'b1011: control <= ((valid) & (~valid_d1)) | ((valid_d1) & (~valid_d2)) | ((valid_d2) & (~valid_d3)) | ((valid_d3) & (~valid_d4)) | ((valid_d4) & (~valid_d5)) | ((valid_d5) & (~valid_d6)) | ((valid_d6) & (~valid_d7)) | ((valid_d7) & (~valid_d8)) | ((valid_d8) & (~valid_d9)) | ((valid_d9) & (~valid_d10)) | ((valid_d10) & (~valid_d11));
	4'b1100: control <= ((valid) & (~valid_d1)) | ((valid_d1) & (~valid_d2)) | ((valid_d2) & (~valid_d3)) | ((valid_d3) & (~valid_d4)) | ((valid_d4) & (~valid_d5)) | ((valid_d5) & (~valid_d6)) | ((valid_d6) & (~valid_d7)) | ((valid_d7) & (~valid_d8)) | ((valid_d8) & (~valid_d9)) | ((valid_d9) & (~valid_d10)) | ((valid_d10) & (~valid_d11)) | ((valid_d11) & (~valid_d12));
	4'b1101: control <= ((valid) & (~valid_d1)) | ((valid_d1) & (~valid_d2)) | ((valid_d2) & (~valid_d3)) | ((valid_d3) & (~valid_d4)) | ((valid_d4) & (~valid_d5)) | ((valid_d5) & (~valid_d6)) | ((valid_d6) & (~valid_d7)) | ((valid_d7) & (~valid_d8)) | ((valid_d8) & (~valid_d9)) | ((valid_d9) & (~valid_d10)) | ((valid_d10) & (~valid_d11)) | ((valid_d11) & (~valid_d12)) | ((valid_d12) & (~valid_d13));
	4'b1110: control <= ((valid) & (~valid_d1)) | ((valid_d1) & (~valid_d2)) | ((valid_d2) & (~valid_d3)) | ((valid_d3) & (~valid_d4)) | ((valid_d4) & (~valid_d5)) | ((valid_d5) & (~valid_d6)) | ((valid_d6) & (~valid_d7)) | ((valid_d7) & (~valid_d8)) | ((valid_d8) & (~valid_d9)) | ((valid_d9) & (~valid_d10)) | ((valid_d10) & (~valid_d11)) | ((valid_d11) & (~valid_d12)) | ((valid_d12) & (~valid_d13)) | ((valid_d13) & (~valid_d14));
	4'b1111: control <= ((valid) & (~valid_d1)) | ((valid_d1) & (~valid_d2)) | ((valid_d2) & (~valid_d3)) | ((valid_d3) & (~valid_d4)) | ((valid_d4) & (~valid_d5)) | ((valid_d5) & (~valid_d6)) | ((valid_d6) & (~valid_d7)) | ((valid_d7) & (~valid_d8)) | ((valid_d8) & (~valid_d9)) | ((valid_d9) & (~valid_d10)) | ((valid_d10) & (~valid_d11)) | ((valid_d11) & (~valid_d12)) | ((valid_d12) & (~valid_d13)) | ((valid_d13) & (~valid_d14)) | ((valid_d14) & (~valid_d15));
	//	5'b10000: control <= ((~valid) & (valid_d1)) | ((~valid_d1) & (valid_d2)) | ((~valid_d2) & (valid_d3)) | ((~valid_d3) & (valid_d4)) | ((~valid_d4) & (valid_d5)) | ((~valid_d5) & (valid_d6)) | ((~valid_d6) & (valid_d7)) | ((~valid_d7) & (valid_d8)) | ((~valid_d8) & (valid_d9)) | ((~valid_d9) & (valid_d10)) | ((~valid_d10) & (valid_d11)) | ((~valid_d11) & (valid_d12)) | ((~valid_d12) & (valid_d13)) | ((~valid_d13) & (valid_d14)) | ((~valid_d14) & (valid_d15)) | ((~valid_d15) & (valid_d16));
endcase

always@(posedge clk)
begin
	if(rst)
	begin
		valid_d1 <= 0;
		valid_d2 <= 0;
		valid_d3 <= 0;
		valid_d4 <= 0;
		valid_d5 <= 0;
		valid_d6 <= 0;
		valid_d7 <= 0;
		valid_d8 <= 0;
		valid_d9 <= 0;	
		valid_d10 <= 0;
		valid_d11 <= 0;
		valid_d12 <= 0;
		valid_d13 <= 0;
		valid_d14 <= 0;
		valid_d15 <= 0;
		valid_d16 <= 0;
   		control_d1 <= 0;
		control_d2 <= 0;
		control_d3 <= 0;
		control_d4 <= 0;
		control_d5 <= 0;
		control_d6 <= 0;
		control_d7 <= 0;
		control_d8 <= 0;
		control_d9 <= 0;
	end
	
	else begin
		valid_d1 <= valid;
		valid_d2 <= valid_d1;
		valid_d3 <= valid_d2;
		valid_d4 <= valid_d3;
		valid_d5 <= valid_d4;
		valid_d6 <= valid_d5;
		valid_d7 <= valid_d6;
		valid_d8 <= valid_d7;
		valid_d9 <= valid_d8;
		valid_d10 <= valid_d9;
		valid_d11 <= valid_d10;
		valid_d12 <= valid_d11;
		valid_d13 <= valid_d12;
		valid_d14 <= valid_d13;
		valid_d15 <= valid_d14;
		valid_d16 <= valid_d15;
		control_d1 <= control;
		control_d2 <= control_d1;
		control_d3 <= control_d2;		
		control_d4 <= control_d3;
		control_d5 <= control_d4;
		control_d6 <= control_d5;
		control_d7 <= control_d6;
		control_d8 <= control_d7;
		control_d9 <= control_d8;
	end
end

endmodule

- - - Updated - - -

I do not understand this line 36 : assign ctrl = control | control_d1;

Besides, to any admins: Why doesn't the syntax colouring tag not working for me ?
 
Last edited by a moderator:

it means ctrl is high for at least 2 clocks.
Instead of asking the internet (on several different forums) for help on this code you dont seem to understand, why not contact the original author? or did you just lift it from somewhere?

Besides, to any admins: Why doesn't the syntax colouring tag not working for me ?

You need to use the syntax tags, not code tags.
 

Hi,

Since the syntax highlighting feature currently is out of order .... it was me that replaced the syntax tags into code tags.

Klaus
 

it means ctrl is high for at least 2 clocks.

Does the above statement mean anything meaningful to you especially with regards to addr on line 45 : addr <= (ctrl) ? pc : inst_addr; ?

Note: pc goes back to 0 when ctrl is deasserted, but inst_addr does not.

Any idea why ?

:bang:
 

No Idea - what does the original author say?
 

@TrickyDicky

I received no reply from the author yet.

The instruction memory module "IMEM" is in the form of dual-port configuration.

I am very curious why pc could be reset to zero while inst_addr could not

:thinker:

- - - Updated - - -

The author replied

Why do you want to reset inst_addr? It’s used for initialization (to know how many instructions are stored in one CPU).
If you don’t reset programmer counter (pc), the CPU won’t execute after one iteration. If you reset inst_addr, you will not be able to generate the control signal.

What do you think ? I do not really comprehend why control signal won't be able to be generated if inst_addr is reset to zero ?
 

I think you should write a testbench for these things, and see if this code is appropriate for your project.
If it isnt, then write your own code.
 

Status
Not open for further replies.

Part and Inventory Search

Welcome to EDABoard.com

Sponsor

Back
Top