Continue to Site

Welcome to EDAboard.com

Welcome to our site! EDAboard.com is an international Electronics Discussion Forum focused on EDA software, circuits, schematics, books, theory, papers, asic, pld, 8051, DSP, Network, RF, Analog Design, PCB, Service Manuals... and a whole lot more! To participate you need to register. Registration is free. Click here to register now.

IR2110 Driver circuit

Status
Not open for further replies.

udaypatil

Newbie level 3
Joined
Feb 23, 2018
Messages
4
Helped
0
Reputation
0
Reaction score
0
Trophy points
1
Activity points
37
I am using IR2110 driver circuit to drive the 100 kHz H-bridge IRF640 MOSFET switches. But as the input voltage to the H-bridge increases (about 25 V) the pulses gets distorted. I have attached the driver circuit. Please help me to solve the problem.
i have attached the circuit diagram below

IR2110 - 7.png
 

Hi,

* please show a scope picture of your "distortions"
* where do you measure the distortions? Node in schematic.
* what is the maximum duty cycle of your circuit?
* you measure without load? No inductive load?
* PCB layout is very important for those "switching power" application. Show your PCB layout. Breadboard will not work.
* use capacitors at the 12V node....as reservoir to quickly charge the bootstrap capacitor.

My hints:
* The benefit of Mosfets is the very low gate current. But the 1k resistor at GS reduces this benefit. A 10k is well sufficient. I know there are many schematics in the internet showing 1k...no one can tell why. With 10k and 100kHz switching frequency a 100n ceramics capacitor is well sufficient. No need for an electrolytics capacitor. I use the 10k / 100nF for more than 25 years now in industrial equippment.

Klaus
 

Hi,
Thank you for your reply..
I am measuring the pulses at the gate and source terminal of the switches.
Duty cycle is 50% to 20%
I am measuring inverter output voltage without load.
i am attaching the images of gating pulses before and after applying input voltage to the inverter,, inverter output voltage and PCB layout.
When input voltage is applied to the inverter, the gating pulses distorts which makes inverter output voltage to distort.
Please reply me the solution for this problem
Capture11.JPG
Capture22.JPG
Capture33.JPG
Capture44.JPG
 

Hi,

Switching power applications ... with wires between drivers and Mosfets are very likely to cause problems.
Keep all connections between driver and Mosfet as short (only millimeters) as possible.
Use a solid GND plane with direct connection of low_side_Mosfet and direct connection of driver_GND.

To verify my words do a simple test:
Connect the scope to the output voltage.
Switch on power and pulses so you see the ringing.
It should be stable.
Now touch the wires (connected G and S of a Mosfet) and move them (apart).
You will see that the ringing changes.

My recommendation:
Go to a Mosfet_manufacturer or driver_manufacturer internet site and look fir application note on how to drive Mosfets correctly.

Klaus
 

The IR2110, is it rated yo 100kHz? it will get hot no doubt. Try buffering each output of the 2110 with a npn-pnp emitter follower - this will help enormously to stop RF noise getting back into the 2110

also at 100kHz your gate drive must be close to the fets, there must be minimum inductance in the power loop of fets else the mid point will go below gnd when the upper fet turns off and possibly destroy the 2110 - they are fragile devices.

- - - Updated - - -

It also appears you have very little solid decoupling on your main converter.
 

When i connect a resistive load at the output of the inverter, the ringing reduces.. So i am not getting the reason for the ringing when inverter output terminals are open
 

The resistive load helps in damping the stray inductance.
 

You really need to build that circuit with a MUCH better layout. You must eliminate those long wires between the drivers and the MOSFETs, and also all other long connections that carry high frequency signals.

A suggested configuration is this: Make two groups of components. Each group contains the two MOSFETs of one half bridge, the driver chip driving them, and the components that go in between. The two MOSFETs are directly together, almost touching each other, and you place at least one nice, very low ESR, very low inductance bypass capacitor across them, from the drain of the upper to the source of the lower MOSFET. Those connections are critical, and should not be longer than a few millimeters, and as wide as possible. So use a circuit board with copper planes for those connections, not narrow tracks.

Those two groups are then arranged on the board so that the sources of the lower MOSFETs end up as close together as possible. This is necessary because your non-isolated driver chips can only tolerate about 5V between those MOSFETs sources and the input-side ground to the chips, and to keep the switching transients there smaller than 5V you really need the negative ends of the half bridges very close together, and very close to the driver chips.

The connections between the driver chips and the MOSFET gates, and the Vs connections to the sources of the upper MOSFETs, are slightly less critical, but not much. Keep them shorter than 5cm total, and if you can, much shorter. Also it's good to keep the gate connections and the returns from the sources to the driver chips, and their bypass capacitors, very close together, either using side-by-side tracks on the board, or better using tracks on both sides of a double sided board, running one atop of the other for as much as possible of the distance.

The layout you used, with long wires between the MOSFETs, and MOSFETs and their drivers, is totally forbidden when working with high frequency! You can use that in linear power supplies, and maybe still in audio amplifiers, but definitely not in a circuit hard-switching high current at 100kHz! To get nice clean switching, you need to cleanly reproduce a lot of harmonics of those 100kHz, and for that you need a flat bandwidth to about 10MHz.

The strong ringing your oscillograms show is generated when the driver chips excite the resonant circuits formed by the MOSFETs' capacitances and your long wires' inductances. You cannot eliminate the MOSFET capacitances, but you can sharply reduce the wiring inductances by following the advice above. That will move the resonances to a much higher frequency, and at that frequency the reactances of the MOSFET capacitances is much lower, so that it can be better damped by the gate resistors, by the RDSon of the MOSFETs, and by stray resistance.

If after all that you still get too much ringing, you can add an RC snubber at each half bridge output. You can choose the resistance of that snubber such that at the full high voltage it takes roughly the same current as the inverter's maximum load, and select a capacitance that has about the same reactance as the resistance value at the ringing frequency. This simplistic method works well enough as long as the ringing frequency is MUCH higher than your switching frequency (say, something like 100 times higher). If it isn't, then you should first bring it up there, by reducing the wiring inductance, bypass ESL, and if that's not enough, chosing FETs having lower capacitances, or as a last resort, reduce the switching frequency.

Another option, elegant but more difficult to design, is to absorb the wiring inductance into the design of a resonant converter.
 

To add to what other posters have already said:
Your ringing waveform shows a 2uS/div timebase, and there are about 10 spurious ringing oscillations within a division.

In other words, the oscillation period is 200 nS, or 5 Mhz frequency.
Definitively a tank circuit formed by parasitic inductances and capacitances.

Follow the recommendations provided above.
 

I have reduced the length of wires and i have also placed a 470 uF capacitor across the bridge.
The ringing is reduced partially for the positive cycle of square wave (output voltage of the inverter), but the ringing remains for the negative cycle of square wave.
Why there is no decoupling capacitor in this driver circuit?
Is there any change to be made in driver circuit to get the neat gating pulses?
Or kindly suggest me with other good gate drivers with its circuit diargam?
 

Hi,

Why there is no decoupling capacitor in this driver circuit?
I assume: because you didn't place one.
You are responsible for stable power supplies.
For the driver IC they are not essential, thus they are not in the datasheet.
But if you want clean signals you should use them ... thus I recommended them.

Is there any change to be made in driver circuit to get the neat gating pulses?
Or kindly suggest me with other good gate drivers with its circuit diargam?
The datasheet and the IC manufacturer (application notes, design notes) tells you how to use them.
We gave recommendations.
Choosing another driver won't bring an improvement.

I don't see your new circuit, but I still think it's not suitable to get the clean signals you expect.

You definitely need very short and very low impedance wiring.
I recommend to use one PCB for Mosfet and driver, a proper GND plane, stable power supplies and good routing of Vs and gate signals.

Klaus
 

Status
Not open for further replies.

Similar threads

Part and Inventory Search

Welcome to EDABoard.com

Sponsor

Back
Top