[SOLVED] PSRR relation with capacitive load

Hi,

I am designing a PMOS LDO using indirect miller feedback. I see that the minimum PSRR is sufficient for high capacitive load (100n). But when the load is reduced to 10p then the minimum PSRR drops to zero. I do not get any explanation regarding this issue in textbook.

(I used the indirect miller feedback such that it does not couple with VDD line at high frequency. i.e, with the nmos cascode load)

Could anybody please give a reasonable explanation?

Thanks.

Your PMOS LDO is a one legged man in an a$$-kicking
contest. That is, there is no real ability to "soak up"
VIN AC activity; the best you can do is choke off the
pass FET leaving its capacitance (Cdb) to pass HF
to the load.

The common-source PMOS is also an entry point with
gain, for VIN HF noise to be amplified if the pass FET
is held linear by the feedback loop.

You can fix some of that by careful gate drive amp
design (eliminating as much as possible, GND "tugging"
on sensitive nodes that are VIN-referred). But you
also might want to consider a Class AB output (NMOS
sink capability) if you need to have, for example, a
very good step response at light loads and load-dump
scenarios.

Miller feedback can be a source of additional problems,
because VIN noise goes directly to Vdg (since load is
basically pinned) and no real Vgs shunt for HF noise
is made. My preference is for shunt compensation at
the gate of the pass FET, for PSRR particularly. This
eats a lot more area of course (no freebie* Miller gain).

* free lunch style, you get area reduction but lose
PSRR when you pick Miller (-only) compensation.
Shunt-C (maybe w/ a HF zero) helps both phase
margin and PSRR; Miller only helps phase margin
in my experience and stands to hurt PSRR or be
no help, at best.