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Single Event Upset in circuit

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Hi,

I am designing a circuit in cadence virtuoso. I want to do the single event upset in a node.

Can anyone tell me the simulation procedure to include it in cadence circuit simulator?

Thanks in advance..
 

I don't think Cadence tools have a "push button" solution to SEU circuit simulation problem.

However, there is a wealth of literature on this subject (just Google it for "single event upset circuit simulation Cadence"), for example:

https://radhome.gsfc.nasa.gov/radhome/papers/tns01_SiGeHBT.pdf

It explains how you can simulate that effect in circuits, but it is not a "push button" or ready-out-of-the-box solution.
 

1) Determine the technology's maximum ion track length.
2) Do the arithmetic to figure out what charge that puts
in the silicon. Assume 100% collection (though it could
be more, if parasitic gain elements are inadequately
suppressed; latchup, even).
3) Put a pulsed current source across whatever PN
junction you are most interested in (leaving the topic
of FDSOI for another decade). Scale its width to the
likely technology timescale (hundred pS for low voltage
logic, nS for medium voltage linears, tens of nS for deep
junction power devices. Scale the amplitude such that
delivered charge is as-calculated in 2). Make the delay
time a user variable (e.g. t_seu) so you can impose the
error stimulus at a time of your choosing (or march it
across a cycle, as sensitivities vary with state).

4) Now, do this for every element in the circuit, each of
its relevant terminal-pair combinations, each different
circuit state.

5) Now inspect for what showed a reaction, and move on
to "why?" and then "whaddyagonnadoaboudit?".

6) Oh, you thought you got them all? Well, check again.
Sometimes the "fix" is just another "victim".

When you want to design unupsettability in a serious
way, you will want to develop some personal tools
(Cadence has nothing for it; Silvaco's native capability
is just clunky). I recommend you hire a consultant ;)

https://www.google.com/search?q="single event transient"+simulation
 

Can we calculate collected charge (Qcoll) from the constants specified in isource i.e, constants such as rise time constant, fall time constant, rise time and fall time.?? I am attaching a image file for your ref.

**broken link removed**

I need to find single event transient in circuit level. So I inserted the above current source in circuit. My question is that how to calculate collected charge (Qcoll) using double exponential function???
 

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In my experience it doesn't matter a lot about the
waveshape, collection happens well faster than device
response to it (at least, in working with sub-GHz analog
and digital).

Don't calculate, simulate. Put your current pulse onto
a large capacitor (say, C=100*q) and look at the delta-V
and do the arithmetic. Then scale the pulse source
property to get a pleasant relation of q(se) to LET.

In real world I fit the "k" factors to match a DFF upset
threshold using a known cell design and beam line data.
However if you are working in non-SOI technologies you
have some additional concerns about charge sharing
and so on, very layout specific.
 

Attachment

Screenshot.png
 

If I want to inject the current pulse same as in attached fig, is it possible in cadence virtuso (with LET values)??

If so, how to give this pulse using cadence virtuoso with LET values???

Screenshot-2.png

{image file taken from book "Soft Errors: from particles to circuits" }
 

To get from LET to delivered charge you need the material
constants (bandgap, density) and the device physical
attributes (type, silicon extents, presence of heavily
doped subsurface features and insulating layers).

The charge-to-produce-upset is just a circuit (+parasitics)
thing. Deciding what constitutes an "upset" in an analog
function is another matter, one application might tolerate
(say) a 2V, 10uS output transient while another might
freak out (especially if further gain and/or pulse stretching
accrue). Even simple output loading can be significant
(especially so, when you are looking at a small, "bare"
block that really would be loaded somehow, but in sims
is not).

I would say an ipulse source with tr=tf=pw=5pS would
match well enough, the waveforms shown. Whether these
are to be believed is questionable, they are shorter than
what I have seen in other papers and given what they
purport to represent, are likely TCAD results and may or
may not properly represent circuit level parasitics outside
the single device mesh of interest (you'd have to review
the remainder of the paper and likely authors' other work
to see what you think of their style and conclusions).
In any case, even these curves show how material
details (doping, geometry, device type) matter to time
and amplitude signatures.

As a rule lighter doped and deeper regions will deliver
more charge, more slowly (as there is more of a remote
component to the collection). The FDSOI SRAM at 5V
or lower, short (truncated) path, high body doping is
going to be a lot more "snappy" than a 200V power
MOSFET with 50um of drift region path length to traverse.
 

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